[llvm] [DAG] fix wrong type check in DAGCombiner::visitSRA (PR #153762)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: woruyu (woruyu)

<details>
<summary>Changes</summary>

Summary
This PR resolves https://github.com/llvm/llvm-project/issues/153543

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Full diff: https://github.com/llvm/llvm-project/pull/153762.diff


1 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+2-2) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d343b644e41cb..245070b8b30be 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10872,8 +10872,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
       // on that type, and the truncate to that type is both legal and free,
       // perform the transform.
       if ((ShiftAmt > 0) &&
-          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
-          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, TruncVT) &&
           TLI.isTruncateFree(VT, TruncVT)) {
         SDValue Amt = DAG.getShiftAmountConstant(ShiftAmt, VT, DL);
         SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,

``````````

</details>


https://github.com/llvm/llvm-project/pull/153762