[llvm] [DAG] fix wrong type check in DAGCombiner::visitSRA (PR #153762)

[via llvm-commits]

https://github.com/woruyu created https://github.com/llvm/llvm-project/pull/153762

Summary
This PR resolves https://github.com/llvm/llvm-project/issues/153543

>From a3ddf7bb1b0d2a5e6ff7879148adc2e87466ebc1 Mon Sep 17 00:00:00 2001
From: woruyu <1214539920 at qq.com>
Date: Fri, 15 Aug 2025 16:06:34 +0800
Subject: [PATCH] [DAG] fix wrong type check in DAGCombiner::visitSRA

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d343b644e41cb..245070b8b30be 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10872,8 +10872,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
       // on that type, and the truncate to that type is both legal and free,
       // perform the transform.
       if ((ShiftAmt > 0) &&
-          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
-          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, TruncVT) &&
           TLI.isTruncateFree(VT, TruncVT)) {
         SDValue Amt = DAG.getShiftAmountConstant(ShiftAmt, VT, DL);
         SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,