[llvm] AMDGPU: Add new VA inline asm constraint for AV registers (PR #152665)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> I actually see the problem with it: the only context it is useful is MFMA. But register class is tied between C and D. If you use this new constraint there RA may allocate v for one and a for another, which does not work. 

It's also useful for load and store. There is no problem, you simply cannot use this constraint for srcC and dst for an MFMA. You are always required to match the operand constraint to the actual instruction you are using, and the instruction encoding does not have an AV register in these operands.

You can use it for srcA and srcB. If you try to misuse this with the wrong operand, you will fail in the assembler (just as you would if you incorrectly specified a VGPR for an operand that requires an SGPR).

https://github.com/llvm/llvm-project/pull/152665