[llvm] AMDGPU: Add new VA inline asm constraint for AV registers (PR #152665)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

I actually see the problem with it: the only context it is useful is MFMA. But register class is tied between C and D. If you use this new constraint there RA may allocate v for one and a for another, which does not work. That is not saying that mfma shall never be an inline asm, there is no reason. The other context is a load feeding mfma, or a store out of it. This is even more troubling to use inline asm on memory ops.

https://github.com/llvm/llvm-project/pull/152665