[llvm] [SystemZ] Support all instruction formats with `.insn` directive (PR #152667)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 8 01:46:15 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Dominik Steenken (dominik-steenken)
<details>
<summary>Changes</summary>
This commit expands the set of supported instruction formats for the `.insn` directive to all published instruction formats. This includes all of the sub-formats (e.g., `RI-a`, `RI-b`, etc.). Sub-formats are indicated by an underscore `_`, followed by the subscript letter of the sub-format in the assembly (e.g. `ri_a` for `RI-a`). Newly supported formats are:
- `I`
- `IE`
- `MII`
- `RI-[abc]`
- `RIE-[abcdefg]`
- `RIL-[abc]`
- `RRD`
- `RRF-[abcde]`
- `RS-[ab]`
- `RSL-[ab]`
- `RSY-[ab]`
- `RX-[ab]`
- `RXY-[abc]`
- `SMI`
- `SS-[abcdef]`
- `VRI-[abcdefghijkl]`
- `VRR-[abcdefghijk]`
- `VRS-[abcd]`
Note that some of these formats have immediate operands which are interpreted inconsistently by the instructions using the format, i.e. some instructions use them as signed immediates, while some use them as unsigned immediates.
This commit adds assembler operand types (`X(8|16|32)Imm`) to support a range check on these immediates that uses the union of the signed and unsigned ranges. So, an 8-bit immediate in a format that is used in both signed and unsigned forms will accept the range [-128..255].
This commit also reorganizes the tests for the `.insn` directives to group them by machine, to mirror the regular assembly tests.
---
Patch is 78.53 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/152667.diff
13 Files Affected:
- (modified) llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (+338-66)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp (+27)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h (+3)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp (+12)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h (+7)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrFormats.td (+446-25)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.td (+356-57)
- (modified) llvm/lib/Target/SystemZ/SystemZOperands.td (+15)
- (added) llvm/test/MC/SystemZ/directive-insn-z13.s (+59)
- (added) llvm/test/MC/SystemZ/directive-insn-z14.s (+33)
- (added) llvm/test/MC/SystemZ/directive-insn-z16.s (+14)
- (added) llvm/test/MC/SystemZ/directive-insn-z17.s (+23)
- (modified) llvm/test/MC/SystemZ/directive-insn.s (+134-2)
``````````diff
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 597ce8eabfeb2..de0c35b55f04a 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -397,11 +397,14 @@ class SystemZOperand : public MCParsedAsmOperand {
bool isU4Imm() const { return isImm(0, 15); }
bool isU8Imm() const { return isImm(0, 255); }
bool isS8Imm() const { return isImm(-128, 127); }
+ bool isX8Imm() const { return isS8Imm() || isU8Imm(); }
bool isU12Imm() const { return isImm(0, 4095); }
bool isU16Imm() const { return isImm(0, 65535); }
bool isS16Imm() const { return isImm(-32768, 32767); }
+ bool isX16Imm() const { return isS16Imm() || isU16Imm(); }
bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
+ bool isX32Imm() const { return isS32Imm() || isU32Imm(); }
bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
};
@@ -663,71 +666,333 @@ struct CompareInsn {
// Table initializing information for parsing the .insn directive.
static struct InsnMatchEntry InsnMatchTable[] = {
- /* Format, Opcode, NumOperands, OperandKinds */
- { "e", SystemZ::InsnE, 1,
- { MCK_U16Imm } },
- { "ri", SystemZ::InsnRI, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
- { "rie", SystemZ::InsnRIE, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
- { "ril", SystemZ::InsnRIL, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
- { "rilu", SystemZ::InsnRILU, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
- { "ris", SystemZ::InsnRIS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
- { "rr", SystemZ::InsnRR, 3,
- { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
- { "rre", SystemZ::InsnRRE, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
- { "rrf", SystemZ::InsnRRF, 5,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
- { "rrs", SystemZ::InsnRRS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
- { "rs", SystemZ::InsnRS, 4,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
- { "rse", SystemZ::InsnRSE, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
- { "rsi", SystemZ::InsnRSI, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
- { "rsy", SystemZ::InsnRSY, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
- { "rx", SystemZ::InsnRX, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxe", SystemZ::InsnRXE, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxf", SystemZ::InsnRXF, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxy", SystemZ::InsnRXY, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
- { "s", SystemZ::InsnS, 2,
- { MCK_U32Imm, MCK_BDAddr64Disp12 } },
- { "si", SystemZ::InsnSI, 3,
- { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
- { "sil", SystemZ::InsnSIL, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
- { "siy", SystemZ::InsnSIY, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
- { "ss", SystemZ::InsnSS, 4,
- { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
- { "sse", SystemZ::InsnSSE, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
- { "ssf", SystemZ::InsnSSF, 4,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
- { "vri", SystemZ::InsnVRI, 6,
- { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
- { "vrr", SystemZ::InsnVRR, 7,
- { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
- MCK_U4Imm } },
- { "vrs", SystemZ::InsnVRS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
- { "vrv", SystemZ::InsnVRV, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
- { "vrx", SystemZ::InsnVRX, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
- { "vsi", SystemZ::InsnVSI, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
-};
+ /* Format, Opcode, NumOperands, OperandKinds */
+ {"e", SystemZ::InsnE, 1, {MCK_U16Imm}},
+ {"i", SystemZ::InsnI, 2, {MCK_U16Imm, MCK_U8Imm}},
+ {"ie", SystemZ::InsnIE, 3, {MCK_U32Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"mii",
+ SystemZ::InsnMII,
+ 4,
+ {MCK_U48Imm, MCK_U4Imm, MCK_PCRel12, MCK_PCRel24}},
+ {"ri", SystemZ::InsnRIa, 3, {MCK_U32Imm, MCK_AnyReg, MCK_S16Imm}},
+ {"ri_a", SystemZ::InsnRIa, 3, {MCK_U32Imm, MCK_AnyReg, MCK_X16Imm}},
+ {"ri_b", SystemZ::InsnRIb, 3, {MCK_U32Imm, MCK_AnyReg, MCK_PCRel16}},
+ {"ri_c", SystemZ::InsnRIc, 3, {MCK_U32Imm, MCK_U4Imm, MCK_PCRel16}},
+ {"rie",
+ SystemZ::InsnRIE,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16}},
+ {"rie_a",
+ SystemZ::InsnRIEa,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_X16Imm, MCK_U4Imm}},
+ {"rie_b",
+ SystemZ::InsnRIEb,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_PCRel16}},
+ {"rie_c",
+ SystemZ::InsnRIEc,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_X8Imm, MCK_U4Imm, MCK_PCRel16}},
+ {"rie_d",
+ SystemZ::InsnRIEd,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_S16Imm, MCK_AnyReg}},
+ {"rie_e",
+ SystemZ::InsnRIEe,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_PCRel16, MCK_AnyReg}},
+ {"rie_f",
+ SystemZ::InsnRIEf,
+ 6,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U8Imm, MCK_U8Imm, MCK_U8Imm}},
+ {"rie_g",
+ SystemZ::InsnRIEg,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_S16Imm, MCK_U4Imm}},
+ {"ril", SystemZ::InsnRIL, 3, {MCK_U48Imm, MCK_AnyReg, MCK_PCRel32}},
+ {"ril_a", SystemZ::InsnRILa, 3, {MCK_U48Imm, MCK_AnyReg, MCK_X32Imm}},
+ {"ril_b", SystemZ::InsnRILb, 3, {MCK_U48Imm, MCK_AnyReg, MCK_PCRel32}},
+ {"ril_c", SystemZ::InsnRILc, 3, {MCK_U48Imm, MCK_U4Imm, MCK_PCRel32}},
+ {"rilu", SystemZ::InsnRILU, 3, {MCK_U48Imm, MCK_AnyReg, MCK_U32Imm}},
+ {"ris",
+ SystemZ::InsnRIS,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_X8Imm, MCK_U4Imm, MCK_BDAddr64Disp12}},
+ {"rr", SystemZ::InsnRR, 3, {MCK_U16Imm, MCK_AnyReg, MCK_AnyReg}},
+ {"rrd",
+ SystemZ::InsnRRD,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg}},
+ {"rre", SystemZ::InsnRRE, 3, {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg}},
+
+ {"rrf",
+ SystemZ::InsnRRF,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_a",
+ SystemZ::InsnRRFa,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_b",
+ SystemZ::InsnRRFb,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_c",
+ SystemZ::InsnRRFc,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_d",
+ SystemZ::InsnRRFd,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_e",
+ SystemZ::InsnRRFe,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_U4Imm}},
+ {"rrs",
+ SystemZ::InsnRRS,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12}},
+ {"rs",
+ SystemZ::InsnRS,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12}},
+ {"rs_a",
+ SystemZ::InsnRSa,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"rs_b",
+ SystemZ::InsnRSb,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U4Imm}},
+ {"rse",
+ SystemZ::InsnRSE,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12}},
+ {"rsi",
+ SystemZ::InsnRSI,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16}},
+ {"rsl_a", SystemZ::InsnRSLa, 2, {MCK_U48Imm, MCK_BDLAddr64Disp12Len4}},
+ {"rsl_b",
+ SystemZ::InsnRSLb,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDLAddr64Disp12Len8, MCK_U4Imm}},
+ {"rsy",
+ SystemZ::InsnRSY,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20}},
+ {"rsy_a",
+ SystemZ::InsnRSYa,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp20, MCK_AnyReg}},
+ {"rsy_b",
+ SystemZ::InsnRSYb,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp20, MCK_U4Imm}},
+ {"rx", SystemZ::InsnRX, 3, {MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rx_a",
+ SystemZ::InsnRXa,
+ 3,
+ {MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rx_b", SystemZ::InsnRXb, 3, {MCK_U32Imm, MCK_U4Imm, MCK_BDXAddr64Disp12}},
+ {"rxe", SystemZ::InsnRXE, 3, {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rxf",
+ SystemZ::InsnRXF,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rxy", SystemZ::InsnRXY, 3, {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
+ {"rxy_a",
+ SystemZ::InsnRXYa,
+ 3,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
+ {"rxy_b",
+ SystemZ::InsnRXYb,
+ 3,
+ {MCK_U48Imm, MCK_U4Imm, MCK_BDXAddr64Disp20}},
+ {"rxy_c",
+ SystemZ::InsnRXYc,
+ 3,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
+ {"s", SystemZ::InsnS, 2, {MCK_U32Imm, MCK_BDAddr64Disp12}},
+ {"si", SystemZ::InsnSI, 3, {MCK_U32Imm, MCK_BDAddr64Disp12, MCK_X8Imm}},
+ {"sil", SystemZ::InsnSIL, 3, {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_X16Imm}},
+ {"siy", SystemZ::InsnSIY, 3, {MCK_U48Imm, MCK_BDAddr64Disp20, MCK_X8Imm}},
+ {"smi",
+ SystemZ::InsnSMI,
+ 4,
+ {MCK_U48Imm, MCK_U4Imm, MCK_PCRel16, MCK_BDAddr64Disp12}},
+ {"ss",
+ SystemZ::InsnSS,
+ 4,
+ {MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"ss_a",
+ SystemZ::InsnSSa,
+ 3,
+ {MCK_U48Imm, MCK_BDLAddr64Disp12Len8, MCK_BDAddr64Disp12}},
+ {"ss_b",
+ SystemZ::InsnSSb,
+ 3,
+ {MCK_U48Imm, MCK_BDLAddr64Disp12Len4, MCK_BDLAddr64Disp12Len4}},
+ {"ss_c",
+ SystemZ::InsnSSc,
+ 4,
+ {MCK_U48Imm, MCK_BDLAddr64Disp12Len4, MCK_BDAddr64Disp12, MCK_U4Imm}},
+ {"ss_d",
+ SystemZ::InsnSSd,
+ 4,
+ {MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"ss_e",
+ SystemZ::InsnSSe,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_AnyReg,
+ MCK_BDAddr64Disp12}},
+ {"ss_f",
+ SystemZ::InsnSSf,
+ 3,
+ {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDLAddr64Disp12Len8}},
+ {"sse",
+ SystemZ::InsnSSE,
+ 3,
+ {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12}},
+ {"ssf",
+ SystemZ::InsnSSF,
+ 4,
+ {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"vri",
+ SystemZ::InsnVRIe,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vri_a",
+ SystemZ::InsnVRIa,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_X16Imm, MCK_U4Imm}},
+ {"vri_b",
+ SystemZ::InsnVRIb,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_U8Imm, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_c",
+ SystemZ::InsnVRIc,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_U16Imm, MCK_VR128, MCK_U4Imm}},
+ {"vri_d",
+ SystemZ::InsnVRId,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_e",
+ SystemZ::InsnVRIe,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U16Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vri_f",
+ SystemZ::InsnVRIf,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_g",
+ SystemZ::InsnVRIg,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_h",
+ SystemZ::InsnVRIh,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_U16Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vri_i",
+ SystemZ::InsnVRIi,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_AnyReg, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_j",
+ SystemZ::InsnVRIj,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_k",
+ SystemZ::InsnVRIk,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm}},
+ {"vri_l",
+ SystemZ::InsnVRIl,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U16Imm}},
+ {"vrr",
+ SystemZ::InsnVRR,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_a",
+ SystemZ::InsnVRRa,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vrr_b",
+ SystemZ::InsnVRRb,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm}},
+ {"vrr_c",
+ SystemZ::InsnVRRc,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_d",
+ SystemZ::InsnVRRd,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_e",
+ SystemZ::InsnVRRe,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_f",
+ SystemZ::InsnVRRf,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_AnyReg, MCK_AnyReg}},
+ {"vrr_g", SystemZ::InsnVRRg, 3, {MCK_U48Imm, MCK_VR128, MCK_U16Imm}},
+ {"vrr_h",
+ SystemZ::InsnVRRh,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm}},
+ {"vrr_i",
+ SystemZ::InsnVRRi,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_U4Imm, MCK_U4Imm}},
+ {"vrr_j",
+ SystemZ::InsnVRRj,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm}},
+ {"vrr_k",
+ SystemZ::InsnVRRk,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm}},
+ {"vrs",
+ SystemZ::InsnVRS,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm}},
+ {"vrs_a",
+ SystemZ::InsnVRSa,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_VR128, MCK_U4Imm}},
+ {"vrs_b",
+ SystemZ::InsnVRSb,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_AnyReg, MCK_U4Imm}},
+ {"vrs_c",
+ SystemZ::InsnVRSc,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_VR128, MCK_U4Imm}},
+ {"vrs_d",
+ SystemZ::InsnVRSd,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"vrv",
+ SystemZ::InsnVRV,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm}},
+ {"vrx",
+ SystemZ::InsnVRX,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm}},
+ {"vsi",
+ SystemZ::InsnVSI,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm}}};
void SystemZOperand::print(raw_ostream &OS, const MCAsmInfo &MAI) const {
switch (Kind) {
@@ -1311,6 +1576,12 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ResTy = parsePCRel32(Operands);
else if (Kind == MCK_PCRel16)
ResTy = parsePCRel16(Operands);
+ else if (Kind == MCK_PCRel12)
+ ResTy = parsePCRel12(Operands);
+ else if (Kind == MCK_PCRel24)
+ ResTy = parsePCRel24(Operands);
+ else if (Kind == MCK_BDLAddr64Disp12Len4 || Kind == MCK_BDLAddr64Disp12Len8)
+ ResTy = parseBDLAddr64(Operands);
else {
// Only remaining operand kind is an immediate.
const MCExpr *Expr;
@@ -1319,7 +1590,6 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
// Expect immediate expression.
if (Parser.parseExpression(Expr))
return Error(StartLoc, "unexpected token in directive");
-
SMLoc EndLoc =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
@@ -1353,6 +1623,8 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ZOperand.addBDXAddrOperands(Inst, 3);
else if (ZOperand.isMem(BDVMem))
ZOperand.addBDVAddrOperands(Inst, 3);
+ else if (ZOperand.isMem(BDLMem))
+ ZOperand.addBDLAddrOperands(Inst, 3);
else if (ZOperand.isMem(LXAMem))
ZOperand.addLXAAddrOperands(Inst, 3);
else if (ZOperand.isImm())
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
index af79070db7b96..d162c1ffcf3a9 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
@@ -118,6 +118,15 @@ void SystemZInstPrinterCommon::printU8ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<8>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX8ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<8>(MI, OpNum, O);
+ else
+ printSImmOperand<8>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printU12ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printUImmOperand<12>(MI, OpNum, O);
@@ -133,6 +142,15 @@ void SystemZInstPrinterCommon::printU16ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<16>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX16ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<16>(MI, OpNum, O);
+ else
+ printSImmOperand<16>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printS32ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printSImmOperand<32>(MI, OpNum, O);
@@ -143,6 +161,15 @@ void SystemZInstPrinterCommon::printU32ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<32>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX32ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<32>(MI, OpNum, O);
+ else
+ printSImmOperand<32>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printU48ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printUImmOperand<48>(MI, OpNum, O);
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
index 427dbba6ad1b4..3d6aa3c12eb52 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
@@ -65,11 +65,14 @@ class SystemZInstPrinterCommon : public MCInstPrinter {
void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU48ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printPCRelOperand(const MCInst *MI, uint64_t Address, int OpNum,
raw_ostream &O);
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
index d692cbed129ca..0cfe4db5cae65 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
@@ -54,6 +54,12 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
return Value;
};
+ auto handleXImmValue = [&](unsigned W) -> uint64_t {
+ if (!checkFixupInRange(minIntN(W), maxUIntN(W)))
+ return 0;
+ return Value;
+ };
+
switch (unsigned(Kind)) {
case SystemZ::FK_390_PC12DBL:
return handlePCRelFixupValue(12);
@@ -91,12 +97,18 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
return handleImmValue(false, 4);
case SystemZ::FK_390_U8Imm:
return handleImmValue(false, 8);
+ ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/152667
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