[llvm] [AArch64][ISel] Subvector extracts can use undef for second EXT input (PR #151729)

[Paul Walker via llvm-commits]

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@@ -15544,7 +15544,9 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
 
     assert(InVT.isScalableVector() && "Unexpected vector type!");
     // Move requested subvector to the start of the vector and try again.
-    SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, InVT, Vec, Vec, Idx);
+    // There's no need for a second input to vector_splice, so use undef there.
+    SDValue Splice =
+        DAG.getNode(ISD::VECTOR_SPLICE, DL, InVT, Vec, DAG.getUNDEF(InVT), Idx);
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paulwalker-arm wrote:

The problem with using `undef` operands is that you loose control over dataflow.  Whilst it frees the register allocator it can lead to situations where the chosen register is the result of an independent long latency instruction (e.g. fsqrt) at which point you end up worse off.

https://github.com/llvm/llvm-project/pull/151729