[llvm] 7cd1ce3 - [SLP]Check vector-like instruction for dominance in copyables

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2025-08-04T06:14:19-07:00
New Revision: 7cd1ce3aa006424d20e95a2a4fe7df7113527976

URL: https://github.com/llvm/llvm-project/commit/7cd1ce3aa006424d20e95a2a4fe7df7113527976
DIFF: https://github.com/llvm/llvm-project/commit/7cd1ce3aa006424d20e95a2a4fe7df7113527976.diff

LOG: [SLP]Check vector-like instruction for dominance in copyables

Need to check if the vector-like instruction is dominated by main
operation in the copyables to prevent broken def-use chain

Fixes #151456

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/vector-like-instr-does-not-dominate.ll

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 5239aac8a8730..0ca25bf891039 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -1329,7 +1329,7 @@ class InstructionsState {
                 // If the copyable instructions comes after MainOp
                 // (non-schedulable, but used in the block) - cannot vectorize
                 // it, will possibly generate use before def.
-                (isVectorLikeInstWithConstOps(I) || !MainOp->comesBefore(I)));
+                !MainOp->comesBefore(I));
       };
 
       return IsNonSchedulableCopyableElement(V);

diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/vector-like-instr-does-not-dominate.ll b/llvm/test/Transforms/SLPVectorizer/X86/vector-like-instr-does-not-dominate.ll
new file mode 100644
index 0000000000000..53640de0812e9
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vector-like-instr-does-not-dominate.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @test(i32 %arg) {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: i32 [[ARG:%.*]]) {
+; CHECK-NEXT:  [[BB:.*]]:
+; CHECK-NEXT:    br label %[[BB14:.*]]
+; CHECK:       [[BB1:.*]]:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <2 x i32> [[TMP11:%.*]], <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT:    br label %[[BB2:.*]]
+; CHECK:       [[BB2]]:
+; CHECK-NEXT:    [[TMP1:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB14]] ], [ zeroinitializer, %[[BB1]] ]
+; CHECK-NEXT:    [[TMP2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[BB14]] ], [ zeroinitializer, %[[BB1]] ]
+; CHECK-NEXT:    [[TMP3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[BB14]] ], [ zeroinitializer, %[[BB1]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = phi <2 x i32> [ [[TMP11]], %[[BB14]] ], [ [[TMP0]], %[[BB1]] ]
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; CHECK-NEXT:    [[ADD10:%.*]] = add i32 [[TMP5]], 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT:    [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP7]], <2 x i32> <i32 2, i32 5>
+; CHECK-NEXT:    br i1 false, label %[[BB14]], label %[[BB11:.*]]
+; CHECK:       [[BB11]]:
+; CHECK-NEXT:    [[TMP9:%.*]] = phi <2 x i32> [ [[TMP1]], %[[BB2]] ]
+; CHECK-NEXT:    br label %[[BB14]]
+; CHECK:       [[BB14]]:
+; CHECK-NEXT:    [[PHI16:%.*]] = phi i32 [ [[ADD10]], %[[BB2]] ], [ 0, %[[BB]] ], [ 0, %[[BB11]] ]
+; CHECK-NEXT:    [[PHI17:%.*]] = phi i32 [ [[TMP6]], %[[BB2]] ], [ 0, %[[BB]] ], [ 0, %[[BB11]] ]
+; CHECK-NEXT:    [[TMP10:%.*]] = phi <2 x i32> [ [[TMP8]], %[[BB2]] ], [ zeroinitializer, %[[BB]] ], [ zeroinitializer, %[[BB11]] ]
+; CHECK-NEXT:    [[TMP11]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[ARG]], i32 1
+; CHECK-NEXT:    switch i32 0, label %[[BB2]] [
+; CHECK-NEXT:      i32 0, label %[[BB1]]
+; CHECK-NEXT:      i32 1, label %[[BB1]]
+; CHECK-NEXT:    ]
+;
+bb:
+  br label %bb14
+
+bb1:
+  %0 = shufflevector <2 x i32> %10, <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 1, i32 3>
+  br label %bb2
+
+bb2:
+  %1 = phi <2 x i32> [ zeroinitializer, %bb14 ], [ zeroinitializer, %bb1 ]
+  %2 = phi <4 x i32> [ zeroinitializer, %bb14 ], [ zeroinitializer, %bb1 ]
+  %3 = phi <4 x i32> [ zeroinitializer, %bb14 ], [ zeroinitializer, %bb1 ]
+  %4 = phi <2 x i32> [ %10, %bb14 ], [ %0, %bb1 ]
+  %5 = extractelement <4 x i32> %3, i32 3
+  %add10 = add i32 %5, 0
+  %6 = extractelement <2 x i32> %1, i32 1
+  %7 = extractelement <4 x i32> %2, i32 2
+  %8 = extractelement <2 x i32> %4, i32 1
+  br i1 false, label %bb14, label %bb11
+
+bb11:
+  %9 = phi <2 x i32> [ %1, %bb2 ]
+  br label %bb14
+
+bb14:
+  %phi15 = phi i32 [ %7, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
+  %phi16 = phi i32 [ %add10, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
+  %phi17 = phi i32 [ %6, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
+  %phi18 = phi i32 [ %8, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
+  %10 = insertelement <2 x i32> <i32 0, i32 poison>, i32 %arg, i32 1
+  switch i32 0, label %bb2 [
+  i32 0, label %bb1
+  i32 1, label %bb1
+  ]
+}
+