[llvm] [AArch64][ISel] Subvector extracts can use undef for second EXT input (PR #151729)

[Gaëtan Bossu via llvm-commits]

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@@ -15544,7 +15544,9 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
 
     assert(InVT.isScalableVector() && "Unexpected vector type!");
     // Move requested subvector to the start of the vector and try again.
-    SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, InVT, Vec, Vec, Idx);
+    // There's no need for a second input to vector_splice, so use undef there.
+    SDValue Splice =
+        DAG.getNode(ISD::VECTOR_SPLICE, DL, InVT, Vec, DAG.getUNDEF(InVT), Idx);
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gbossu wrote:

Oh, I guess I still need to reprogram my brain, because of course aarch64 CPUs have HW interlocks... So even if there is no logical dependency due to the `undef`, the HW will certainly see a dependency and wait for the register to be available.

I think I have to agree with you then, it's probably better to avoid `undef` and unexpected dependencies.

https://github.com/llvm/llvm-project/pull/151729