[llvm] [RISCV] Relax destination instruction dag operand matching in CompresInstEmitter (PR #148660)

[Craig Topper via llvm-commits]

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@@ -171,10 +171,6 @@ bool CompressInstEmitter::validateTypes(const Record *DagOpType,
                                         bool IsSourceInst) {
   if (DagOpType == InstOpType)
     return true;
-  // Only source instruction operands are allowed to not match Input Dag
-  // operands.
-  if (!IsSourceInst)
-    return false;
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topperc wrote:

I think both compressInst and uncompressInst check the register belongs to the register class of the instruction we're transforming to. I don't think the register subclass check in tablegen is strictly necessary other than to verify you aren't writing impossible patterns.

Not directly related to this patch. I think the compressInst and uncompressInst runtime checks should be using the register class from the DAG pattern not from the final instruction. As it stands now we can't unify C_ADDI and C_ADDI_HINT because we can't express that C_ADDI with x0 destination should not uncompress to ADDI.

https://github.com/llvm/llvm-project/pull/148660