[llvm] [RISCV] Relax destination instruction dag operand matching in CompresInstEmitter (PR #148660)

[Sam Elliott via llvm-commits]

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@@ -171,10 +171,6 @@ bool CompressInstEmitter::validateTypes(const Record *DagOpType,
                                         bool IsSourceInst) {
   if (DagOpType == InstOpType)
     return true;
-  // Only source instruction operands are allowed to not match Input Dag
-  // operands.
-  if (!IsSourceInst)
-    return false;
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lenary wrote:

While I agree with relaxing this, I am not sure the rest of the conditions should be identical, as I think there's some co-/contra-variance thing happening here, and the subclass checks need to be in the other direction for source instructions. I recall we talked about this, but I don't recall the conclusion we came to then.

https://github.com/llvm/llvm-project/pull/148660