[llvm] [RISCV] Relax destination instruction dag operand matching in CompresInstEmitter (PR #148660)

[Sam Elliott via llvm-commits]

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@@ -171,10 +171,6 @@ bool CompressInstEmitter::validateTypes(const Record *DagOpType,
                                         bool IsSourceInst) {
   if (DagOpType == InstOpType)
     return true;
-  // Only source instruction operands are allowed to not match Input Dag
-  // operands.
-  if (!IsSourceInst)
-    return false;
----------------
lenary wrote:

> Not directly related to this patch. I think the compressInst and uncompressInst runtime checks should be using the register class from the DAG pattern not from the final instruction. As it stands now we can't unify C_ADDI and C_ADDI_HINT because we can't express that C_ADDI with x0 destination should not uncompress to ADDI.

Aha, this might be the covariance/contravariance thing I would expect. I guess the problem is "how do you uncompress, validly" if you only use the dag pattern, but that's not an issue for compression.

I'll defer to Craig's LGTM here. Don't consider my comments blocking.

https://github.com/llvm/llvm-project/pull/148660