[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (PR #148121)

[Sam Elliott via llvm-commits]

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@@ -1485,6 +1501,36 @@ def : QCIMVCCIPat <SETLT,  QC_MVLTI, simm5>;
 def : QCIMVCCIPat <SETULT, QC_MVLTUI, uimm5>;
 }
 
+let Predicates = [HasVendorXqcicli, HasVendorXqcicsOrXqcicm, IsRV32] in {
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lenary wrote:

It's complex and a comment would be helpful, so maybe I'll sketch one out.

These patterns are written using `select`, which is normally not legal on RISC-V. We cannot mark `select` as legal when we only have `xqcicli`, because we cannot isel a select of a condition and two arbitrary xlen values (in registers) when we only have `xqcicli` (there is no instruction in the extension that can do so).

But we only care about codegen for configs where we have both xqcics/xqcicm and xqcicli - we can sort-of see xqcicli as an optimisation of the other two. If we have either of the other two, then we have marked `select` as legal and we can lower a `select` with a condition and two xlen values (in registers).

These patterns would only be used if we have one of the other two extensions, so make that clear with their predicates.

https://github.com/llvm/llvm-project/pull/148121