[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (PR #148121)

[Sudharsan Veeravalli via llvm-commits]

================
@@ -0,0 +1,717 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test that we are able to generate the Xqcicli instructions
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli,+experimental-xqcics -verify-machineinstrs < %s \
----------------
svs-quic wrote:

What about a RUN line with only xqcicli enable?

https://github.com/llvm/llvm-project/pull/148121