[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (PR #148121)

[Sam Elliott via llvm-commits]

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@@ -0,0 +1,717 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test that we are able to generate the Xqcicli instructions
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli,+experimental-xqcics -verify-machineinstrs < %s \
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lenary wrote:

See the other comment above, but the thing here is we need at least one of xqcics or xqcicm, for select to be marked legal and the patterns to be able to apply.

https://github.com/llvm/llvm-project/pull/148121