[llvm] [RISCV] Add ISel patterns for Xqciac QC_SHLADD instruction (PR #148256)

[Sam Elliott via llvm-commits]

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@@ -15056,7 +15059,10 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
   // Skip if SH1ADD/SH2ADD/SH3ADD are not applicable.
   int64_t Bits = std::min(C0, C1);
   int64_t Diff = std::abs(C0 - C1);
-  if (Diff != 1 && Diff != 2 && Diff != 3)
+  if (Diff != 1 && Diff != 2 && Diff != 3 && !Subtarget.hasVendorXqciac())
+    return SDValue();
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lenary wrote:

Presumably if we only have `xqciac`, then we cannot handle Diff in [1,2,3]. I don't know if this is worth handling properly, because the configurations we care about also have zba.

In the xqcicli patch, I asked for the predicates on those patterns to be `(xqcicm || xqcics) && xqcicli`, because we wanted xqcicli to use `select`, but select was only being marked as legal when we had one of xqcicm or xqcics - because `xqcicli` cannot lower some forms of select.

I wonder if we should do the same here - mark the `xqciac` shladd patterns as requiring both `zba` and `xqciac`, and assuming everywhere that if we are going to codegen `xqciac` then we need to also have `zba`.

This might not be very clear, I can talk it over with you if you want.

https://github.com/llvm/llvm-project/pull/148256