[llvm] [RISCV] Add ISel patterns for Xqciac QC_SHLADD instruction (PR #148256)

[Sam Elliott via llvm-commits]

================
@@ -15056,7 +15059,10 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
   // Skip if SH1ADD/SH2ADD/SH3ADD are not applicable.
   int64_t Bits = std::min(C0, C1);
   int64_t Diff = std::abs(C0 - C1);
-  if (Diff != 1 && Diff != 2 && Diff != 3)
+  if (Diff != 1 && Diff != 2 && Diff != 3 && !Subtarget.hasVendorXqciac())
+    return SDValue();
+
+  if (!Diff || Diff > 31)
----------------
lenary wrote:

```suggestion
  if (Diff != 0 || Diff > 31)
```
This is a bit clearer which immediates are covered. 

https://github.com/llvm/llvm-project/pull/148256