[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (PR #148121)

[Sudharsan Veeravalli via llvm-commits]

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@@ -1485,6 +1501,36 @@ def : QCIMVCCIPat <SETLT,  QC_MVLTI, simm5>;
 def : QCIMVCCIPat <SETULT, QC_MVLTUI, uimm5>;
 }
 
+let Predicates = [HasVendorXqcicli, HasVendorXqcicsOrXqcicm, IsRV32] in {
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svs-quic wrote:

Why do we need this?

https://github.com/llvm/llvm-project/pull/148121