[llvm] 6670fe2 - ARMMCCodeEmitter: Set PCRel at fixup creation
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 17:08:30 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T17:08:25-07:00
New Revision: 6670fe2ed498f70221e4b444aa1d08d0d47e8577
URL: https://github.com/llvm/llvm-project/commit/6670fe2ed498f70221e4b444aa1d08d0d47e8577
DIFF: https://github.com/llvm/llvm-project/commit/6670fe2ed498f70221e4b444aa1d08d0d47e8577.diff
LOG: ARMMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.
Added:
Modified:
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 5a8080db12629..d360be8aa1759 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -70,44 +70,34 @@ MCFixupKindInfo ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
// ARMFixupKinds.h.
//
// Name Offset (bits) Size (bits) Flags
- {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_arm_ldst_pcrel_12", 0, 32, 0},
{"fixup_t2_ldst_pcrel_12", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_pcrel_10", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_pcrel_9", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_pcrel_10_unscaled", 0, 32, 0},
+ {"fixup_arm_pcrel_10", 0, 32, 0},
+ {"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_pcrel_9", 0, 32, 0},
+ {"fixup_t2_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_ldst_abs_12", 0, 32, 0},
{"fixup_thumb_adr_pcrel_10", 0, 8,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_adr_pcrel_12", 0, 32, 0},
{"fixup_t2_adr_pcrel_12", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_condbranch", 0, 24, 0},
+ {"fixup_arm_uncondbranch", 0, 24, 0},
+ {"fixup_t2_condbranch", 0, 32, 0},
+ {"fixup_t2_uncondbranch", 0, 32, 0},
+ {"fixup_arm_thumb_br", 0, 16, 0},
+ {"fixup_arm_uncondbl", 0, 24, 0},
+ {"fixup_arm_condbl", 0, 24, 0},
+ {"fixup_arm_blx", 0, 24, 0},
+ {"fixup_arm_thumb_bl", 0, 32, 0},
{"fixup_arm_thumb_blx", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_thumb_cp", 0, 8,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_thumb_cb", 0, 16, 0},
+ {"fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_thumb_bcc", 0, 8, 0},
// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
// - 19.
{"fixup_arm_movt_hi16", 0, 20, 0},
@@ -120,56 +110,47 @@ MCFixupKindInfo ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_arm_thumb_lower_0_7", 0, 8, 0},
{"fixup_arm_mod_imm", 0, 12, 0},
{"fixup_t2_so_imm", 0, 26, 0},
- {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_bf_branch", 0, 32, 0},
+ {"fixup_bf_target", 0, 32, 0},
+ {"fixup_bfl_target", 0, 32, 0},
+ {"fixup_bfc_target", 0, 32, 0},
{"fixup_bfcsel_else_target", 0, 32, 0},
- {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
+ {"fixup_wls", 0, 32, 0},
+ {"fixup_le", 0, 32, 0},
+ };
const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
// This table *must* be in the order that the fixup_* kinds are defined in
// ARMFixupKinds.h.
//
// Name Offset (bits) Size (bits) Flags
- {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_arm_ldst_pcrel_12", 0, 32, 0},
{"fixup_t2_ldst_pcrel_12", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_pcrel_10", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_pcrel_9", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_pcrel_10_unscaled", 0, 32, 0},
+ {"fixup_arm_pcrel_10", 0, 32, 0},
+ {"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_pcrel_9", 0, 32, 0},
+ {"fixup_t2_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_ldst_abs_12", 0, 32, 0},
{"fixup_thumb_adr_pcrel_10", 8, 8,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_adr_pcrel_12", 0, 32, 0},
{"fixup_t2_adr_pcrel_12", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_condbranch", 8, 24, 0},
+ {"fixup_arm_uncondbranch", 8, 24, 0},
+ {"fixup_t2_condbranch", 0, 32, 0},
+ {"fixup_t2_uncondbranch", 0, 32, 0},
+ {"fixup_arm_thumb_br", 0, 16, 0},
+ {"fixup_arm_uncondbl", 8, 24, 0},
+ {"fixup_arm_condbl", 8, 24, 0},
+ {"fixup_arm_blx", 8, 24, 0},
+ {"fixup_arm_thumb_bl", 0, 32, 0},
{"fixup_arm_thumb_blx", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_arm_thumb_cp", 8, 8,
- MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
- {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_thumb_cb", 0, 16, 0},
+ {"fixup_arm_thumb_cp", 8, 8, MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_thumb_bcc", 8, 8, 0},
// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
// - 19.
{"fixup_arm_movt_hi16", 12, 20, 0},
@@ -182,13 +163,14 @@ MCFixupKindInfo ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_arm_thumb_lower_0_7", 24, 8, 0},
{"fixup_arm_mod_imm", 20, 12, 0},
{"fixup_t2_so_imm", 26, 6, 0},
- {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_bf_branch", 0, 32, 0},
+ {"fixup_bf_target", 0, 32, 0},
+ {"fixup_bfl_target", 0, 32, 0},
+ {"fixup_bfc_target", 0, 32, 0},
{"fixup_bfcsel_else_target", 0, 32, 0},
- {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
+ {"fixup_wls", 0, 32, 0},
+ {"fixup_le", 0, 32, 0},
+ };
// Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
// any extra processing.
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 5c1c569ddcd3d..fa8bd267e5823 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -313,41 +313,12 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &ST) const {
- const MCOperand &MO = MI.getOperand(Op);
-
- // Support for fixups (MCFixup)
- if (MO.isExpr()) {
- const MCExpr *Expr = MO.getExpr();
- // Fixups resolve to plain values that need to be encoded.
- MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
- Fixups.push_back(MCFixup::create(0, Expr, Kind));
- return 0;
- }
-
- // Immediate is already in its encoded format
- return MO.getImm();
- }
+ const MCSubtargetInfo &ST) const;
/// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(Op);
-
- // Support for fixups (MCFixup)
- if (MO.isExpr()) {
- const MCExpr *Expr = MO.getExpr();
- // Fixups resolve to plain values that need to be encoded.
- MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
- Fixups.push_back(MCFixup::create(0, Expr, Kind));
- return 0;
- }
- unsigned SoImm = MO.getImm();
- unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
- assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
- return Encoded;
- }
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
@@ -462,6 +433,44 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
} // end anonymous namespace
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+ const MCExpr *Value, uint16_t Kind) {
+ bool PCRel = false;
+ switch (Kind) {
+ case ARM::fixup_arm_ldst_pcrel_12:
+ case ARM::fixup_t2_ldst_pcrel_12:
+ case ARM::fixup_arm_pcrel_10_unscaled:
+ case ARM::fixup_arm_pcrel_10:
+ case ARM::fixup_t2_pcrel_10:
+ case ARM::fixup_arm_pcrel_9:
+ case ARM::fixup_t2_pcrel_9:
+ case ARM::fixup_thumb_adr_pcrel_10:
+ case ARM::fixup_arm_adr_pcrel_12:
+ case ARM::fixup_t2_adr_pcrel_12:
+ case ARM::fixup_arm_condbranch:
+ case ARM::fixup_arm_uncondbranch:
+ case ARM::fixup_t2_condbranch:
+ case ARM::fixup_t2_uncondbranch:
+ case ARM::fixup_arm_thumb_br:
+ case ARM::fixup_arm_uncondbl:
+ case ARM::fixup_arm_condbl:
+ case ARM::fixup_arm_blx:
+ case ARM::fixup_arm_thumb_bl:
+ case ARM::fixup_arm_thumb_blx:
+ case ARM::fixup_arm_thumb_cb:
+ case ARM::fixup_arm_thumb_cp:
+ case ARM::fixup_arm_thumb_bcc:
+ case ARM::fixup_bf_branch:
+ case ARM::fixup_bf_target:
+ case ARM::fixup_bfl_target:
+ case ARM::fixup_bfc_target:
+ case ARM::fixup_wls:
+ case ARM::fixup_le:
+ PCRel = true;
+ }
+ Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
/// instructions, and rewrite them to their Thumb2 form if we are currently in
/// Thumb2 mode.
@@ -616,7 +625,7 @@ static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected branch target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(FixupKind);
- Fixups.push_back(MCFixup::create(0, Expr, Kind));
+ addFixup(Fixups, 0, Expr, Kind);
// All of the information is in the fixup.
return 0;
@@ -979,7 +988,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
isAdd = false; // 'U' bit is set as part of the fixup.
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
- Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind));
+ addFixup(Fixups, 0, MO1.getExpr(), Kind);
}
} else if (MO.isExpr()) {
Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
@@ -989,7 +998,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
else
Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
+ addFixup(Fixups, 0, MO.getExpr(), Kind);
++MCNumCPRelocations;
} else {
@@ -1114,7 +1123,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
- Fixups.push_back(MCFixup::create(0, Expr, Kind));
+ addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
} else
@@ -1251,7 +1260,7 @@ uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
break;
}
- Fixups.push_back(MCFixup::create(0, E, Kind));
+ addFixup(Fixups, 0, E, Kind);
return 0;
}
// If the expression doesn't have :upper16:, :lower16: on it, it's just a
@@ -1373,7 +1382,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
- Fixups.push_back(MCFixup::create(0, Expr, Kind));
+ addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
return (Rn << 9) | (1 << 13);
@@ -1455,7 +1464,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
else
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
- Fixups.push_back(MCFixup::create(0, Expr, Kind));
+ addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
} else {
@@ -1495,7 +1504,7 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
else
Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
- Fixups.push_back(MCFixup::create(0, Expr, Kind));
+ addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
} else {
@@ -1511,6 +1520,43 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
return Binary;
}
+unsigned ARMMCCodeEmitter::getModImmOpValue(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &ST) const {
+ const MCOperand &MO = MI.getOperand(Op);
+
+ // Support for fixups (MCFixup)
+ if (MO.isExpr()) {
+ const MCExpr *Expr = MO.getExpr();
+ // Fixups resolve to plain values that need to be encoded.
+ MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
+ addFixup(Fixups, 0, Expr, Kind);
+ return 0;
+ }
+
+ // Immediate is already in its encoded format
+ return MO.getImm();
+}
+
+unsigned ARMMCCodeEmitter::getT2SOImmOpValue(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(Op);
+
+ // Support for fixups (MCFixup)
+ if (MO.isExpr()) {
+ const MCExpr *Expr = MO.getExpr();
+ // Fixups resolve to plain values that need to be encoded.
+ MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
+ addFixup(Fixups, 0, Expr, Kind);
+ return 0;
+ }
+ unsigned SoImm = MO.getImm();
+ unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
+ assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
+ return Encoded;
+}
+
unsigned ARMMCCodeEmitter::
getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
@@ -1950,7 +1996,7 @@ ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
const MCExpr *DiffExpr = MCBinaryExpr::createSub(
MO.getExpr(), BranchMO.getExpr(), CTX);
MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
- Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind));
+ addFixup(Fixups, 0, DiffExpr, Kind);
return 0;
}
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