[llvm] 8bb4e53 - PPCMCCodeEmitter: Set PCRel at fixup creation
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 17:21:43 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T17:21:38-07:00
New Revision: 8bb4e534284df9405c081d2570613f944042519f
URL: https://github.com/llvm/llvm-project/commit/8bb4e534284df9405c081d2570613f944042519f
DIFF: https://github.com/llvm/llvm-project/commit/8bb4e534284df9405c081d2570613f944042519f.diff
LOG: PPCMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.
Added:
Modified:
llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index 2bd2092dfeda6..671b60aaa9d52 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -149,30 +149,32 @@ class PPCAsmBackend : public MCAsmBackend {
} // end anonymous namespace
MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
+ // clang-format off
const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
// name offset bits flags
- {"fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_br24", 6, 24, 0},
+ {"fixup_ppc_br24_notoc", 6, 24, 0},
+ {"fixup_ppc_brcond14", 16, 14, 0},
{"fixup_ppc_br24abs", 6, 24, 0},
{"fixup_ppc_brcond14abs", 16, 14, 0},
{"fixup_ppc_half16", 0, 16, 0},
{"fixup_ppc_half16ds", 0, 14, 0},
- {"fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_pcrel34", 0, 34, 0},
{"fixup_ppc_imm34", 0, 34, 0},
{"fixup_ppc_nofixup", 0, 0, 0}};
const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
// name offset bits flags
- {"fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_br24", 2, 24, 0},
+ {"fixup_ppc_br24_notoc", 2, 24, 0},
+ {"fixup_ppc_brcond14", 2, 14, 0},
{"fixup_ppc_br24abs", 2, 24, 0},
{"fixup_ppc_brcond14abs", 2, 14, 0},
{"fixup_ppc_half16", 0, 16, 0},
{"fixup_ppc_half16ds", 2, 14, 0},
- {"fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_pcrel34", 0, 34, 0},
{"fixup_ppc_imm34", 0, 34, 0},
{"fixup_ppc_nofixup", 0, 0, 0}};
+ // clang-format on
// Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
// do not require any extra processing.
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index fc145f37fae95..af8628f442cc7 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -39,6 +39,19 @@ MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
return new PPCMCCodeEmitter(MCII, Ctx);
}
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+ const MCExpr *Value, uint16_t Kind) {
+ bool PCRel = false;
+ switch (Kind) {
+ case PPC::fixup_ppc_br24:
+ case PPC::fixup_ppc_br24_notoc:
+ case PPC::fixup_ppc_brcond14:
+ case PPC::fixup_ppc_pcrel34:
+ PCRel = true;
+ }
+ Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
unsigned PPCMCCodeEmitter::
getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
@@ -49,10 +62,9 @@ getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- (isNoTOCCallInstr(MI)
- ? (MCFixupKind)PPC::fixup_ppc_br24_notoc
- : (MCFixupKind)PPC::fixup_ppc_br24)));
+ addFixup(
+ Fixups, 0, MO.getExpr(),
+ (isNoTOCCallInstr(MI) ? PPC::fixup_ppc_br24_notoc : PPC::fixup_ppc_br24));
return 0;
}
@@ -157,8 +169,7 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_brcond14));
+ addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_brcond14);
return 0;
}
@@ -170,8 +181,7 @@ getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_br24abs));
+ addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_br24abs);
return 0;
}
@@ -183,8 +193,7 @@ getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_brcond14abs));
+ addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_brcond14abs);
return 0;
}
@@ -205,8 +214,7 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the immediate field.
- Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_half16));
+ addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), PPC::fixup_ppc_half16);
return 0;
}
@@ -220,7 +228,7 @@ uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the immediate field.
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
+ addFixup(Fixups, 0, MO.getExpr(), Fixup);
return 0;
}
@@ -248,8 +256,7 @@ unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
// Add a fixup for the displacement field.
- Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_half16));
+ addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), PPC::fixup_ppc_half16);
return 0;
}
@@ -262,8 +269,8 @@ PPCMCCodeEmitter::getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
// Add a fixup for the displacement field.
- Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_half16ds));
+ addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(),
+ PPC::fixup_ppc_half16ds);
return 0;
}
@@ -279,8 +286,8 @@ PPCMCCodeEmitter::getDispRIX16Encoding(const MCInst &MI, unsigned OpNo,
}
// Otherwise add a fixup for the displacement field.
- Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_half16dq));
+ addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(),
+ PPC::fixup_ppc_half16dq);
return 0;
}
@@ -335,9 +342,7 @@ PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
"specifier must be S_PCREL, S_GOT_PCREL, S_GOT_TLSGD_PCREL, "
"S_GOT_TLSLD_PCREL, or S_GOT_TPREL_PCREL");
// Generate the fixup for the relocation.
- Fixups.push_back(
- MCFixup::create(0, Expr,
- static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
+ addFixup(Fixups, 0, Expr, PPC::fixup_ppc_pcrel34);
// Put zero in the location of the immediate. The linker will fill in the
// correct value based on the relocation.
return 0;
@@ -369,9 +374,7 @@ PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
getSpecifier(SRE) == PPC::S_GOT_PCREL) &&
"VariantKind must be VK_PCREL or VK_GOT_PCREL");
// Generate the fixup for the relocation.
- Fixups.push_back(
- MCFixup::create(0, Expr,
- static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
+ addFixup(Fixups, 0, Expr, PPC::fixup_ppc_pcrel34);
// Put zero in the location of the immediate. The linker will fill in the
// correct value based on the relocation.
return 0;
@@ -431,8 +434,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
const MCExpr *Expr = MO.getExpr();
const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
bool IsPCRel = getSpecifier(SRE) == PPC::S_TLS_PCREL;
- Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
- (MCFixupKind)PPC::fixup_ppc_nofixup));
+ addFixup(Fixups, IsPCRel ? 1 : 0, Expr, PPC::fixup_ppc_nofixup);
const Triple &TT = STI.getTargetTriple();
bool isPPC64 = TT.isPPC64();
return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
@@ -445,8 +447,7 @@ unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
// (__tls_get_addr), which we create via getDirectBrEncoding as usual,
// and one for the TLSGD or TLSLD symbol, which is emitted here.
const MCOperand &MO = MI.getOperand(OpNo+1);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_nofixup));
+ addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_nofixup);
return getDirectBrEncoding(MI, OpNo, Fixups, STI);
}
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