[llvm] 73c03b9 - XtensaMCCodeEmitter: Set PCRel at fixup creation

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2025-07-04T16:57:04-07:00
New Revision: 73c03b92cec643a31327b2320207a3599970470f

URL: https://github.com/llvm/llvm-project/commit/73c03b92cec643a31327b2320207a3599970470f
DIFF: https://github.com/llvm/llvm-project/commit/73c03b92cec643a31327b2320207a3599970470f.diff

LOG: XtensaMCCodeEmitter: Set PCRel at fixup creation

Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.

Added: 
    

Modified: 
    llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
    llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
index 3343617daaba4..54861b7a0ad65 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
@@ -53,17 +53,16 @@ class XtensaAsmBackend : public MCAsmBackend {
 MCFixupKindInfo XtensaAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
   const static MCFixupKindInfo Infos[Xtensa::NumTargetFixupKinds] = {
       // name                     offset bits  flags
-      {"fixup_xtensa_branch_6", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_xtensa_branch_8", 16, 8, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_xtensa_branch_12", 12, 12, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_xtensa_jump_18", 6, 18, MCFixupKindInfo::FKF_IsPCRel},
+      {"fixup_xtensa_branch_6", 0, 16, 0},
+      {"fixup_xtensa_branch_8", 16, 8, 0},
+      {"fixup_xtensa_branch_12", 12, 12, 0},
+      {"fixup_xtensa_jump_18", 6, 18, 0},
       {"fixup_xtensa_call_18", 6, 18,
-       MCFixupKindInfo::FKF_IsPCRel |
-           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+       MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_xtensa_l32r_16", 8, 16,
-       MCFixupKindInfo::FKF_IsPCRel |
-           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-      {"fixup_xtensa_loop_8", 16, 8, MCFixupKindInfo::FKF_IsPCRel}};
+       MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+      {"fixup_xtensa_loop_8", 16, 8, 0},
+  };
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);

diff  --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
index 5228f84f05d4a..bd4d4ebd2a729 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
@@ -150,6 +150,22 @@ MCCodeEmitter *llvm::createXtensaMCCodeEmitter(const MCInstrInfo &MCII,
   return new XtensaMCCodeEmitter(MCII, Ctx, true);
 }
 
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+                     const MCExpr *Value, uint16_t Kind) {
+  bool PCRel = false;
+  switch (Kind) {
+  case Xtensa::fixup_xtensa_branch_6:
+  case Xtensa::fixup_xtensa_branch_8:
+  case Xtensa::fixup_xtensa_branch_12:
+  case Xtensa::fixup_xtensa_jump_18:
+  case Xtensa::fixup_xtensa_call_18:
+  case Xtensa::fixup_xtensa_l32r_16:
+  case Xtensa::fixup_xtensa_loop_8:
+    PCRel = true;
+  }
+  Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
 void XtensaMCCodeEmitter::encodeInstruction(const MCInst &MI,
                                             SmallVectorImpl<char> &CB,
                                             SmallVectorImpl<MCFixup> &Fixups,
@@ -195,8 +211,7 @@ XtensaMCCodeEmitter::getJumpTargetEncoding(const MCInst &MI, unsigned int OpNum,
     return MO.getImm();
 
   const MCExpr *Expr = MO.getExpr();
-  Fixups.push_back(
-      MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_jump_18)));
+  addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_jump_18);
   return 0;
 }
 
@@ -213,17 +228,14 @@ uint32_t XtensaMCCodeEmitter::getBranchTargetEncoding(
   case Xtensa::BGEZ:
   case Xtensa::BLTZ:
   case Xtensa::BNEZ:
-    Fixups.push_back(
-        MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_12)));
+    addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_branch_12);
     return 0;
   case Xtensa::BEQZ_N:
   case Xtensa::BNEZ_N:
-    Fixups.push_back(
-        MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_6)));
+    addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_branch_6);
     return 0;
   default:
-    Fixups.push_back(
-        MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_8)));
+    addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_branch_8);
     return 0;
   }
 }
@@ -240,8 +252,7 @@ XtensaMCCodeEmitter::getLoopTargetEncoding(const MCInst &MI, unsigned int OpNum,
 
   const MCExpr *Expr = MO.getExpr();
 
-  Fixups.push_back(
-      MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_loop_8)));
+  addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_loop_8);
   return 0;
 }
 
@@ -261,8 +272,7 @@ XtensaMCCodeEmitter::getCallEncoding(const MCInst &MI, unsigned int OpNum,
 
   assert((MO.isExpr()) && "Unexpected operand value!");
   const MCExpr *Expr = MO.getExpr();
-  Fixups.push_back(
-      MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_call_18)));
+  addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_call_18);
   return 0;
 }
 
@@ -281,8 +291,7 @@ XtensaMCCodeEmitter::getL32RTargetEncoding(const MCInst &MI, unsigned OpNum,
 
   assert((MO.isExpr()) && "Unexpected operand value!");
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
-                                   MCFixupKind(Xtensa::fixup_xtensa_l32r_16)));
+  addFixup(Fixups, 0, MO.getExpr(), Xtensa::fixup_xtensa_l32r_16);
   return 0;
 }