[llvm] [RISCV] Support RVV register overlapping constraints (PR #145004)

[Pengcheng Wang via llvm-commits]

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@@ -1040,3 +1047,221 @@ bool RISCVRegisterInfo::getRegAllocationHints(
 
   return BaseImplRetVal;
 }
+
+unsigned RISCVRegisterInfo::getMCRegIndex(MCRegister Reg,
+                                          const MachineRegisterInfo *MRI) {
+  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
+  return TRI->getEncodingValue(Reg);
+}
+
+unsigned RISCVRegisterInfo::getMCRegLMUL(MCRegister Reg) {
+  if (RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg))
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wangpc-pp wrote:

Get it from RISCVRI::getLMul?

https://github.com/llvm/llvm-project/pull/145004