[llvm] [RISCV] Support RVV register overlapping constraints (PR #145004)

[Pengcheng Wang via llvm-commits]

https://github.com/wangpc-pp commented:

Just FYI, we have done an evaluation before (the overlapping constraints in RVV are not reasonable for OoO cores with renaming so we wanted to know how big the impact is):

1. We removed all the overlapping constraints in TableGen.
2. Compiled SPEC CPU 2017 and llvm-testsuite.
3. Collected the spill/reload statistics. No COPY data because we think it doesn't matter.

The benchmarks were compiled with `-mllvm -riscv-v-register-bit-width-lmul=N` to control the register pressure when vectorizing, and the baselines were compiled with the same commands but with an unmodified compiler (with RA early-clobber constraints).

The result is:
| llvm-testsuite | Spill  | Reload |
|----------------|--------|--------|
| M1             | -0.46% | -0.14% |
| M2             | -0.65% | -0.29% |
| M4             | -0.64% | +0.10% |
| M8             | -0.70% | +0.23% |

| SPEC CPU 2017 | Spill  | Reload |
|---------------|--------|--------|
| M1            | -0.01% | -0.0%  |
| M2            | -0.10% | -0.10% |
| M4            | -0.40% | -0.40% |
| M8            | -0.60% | -0.30% |

----

I won't interpret some of the result here (I don't know why there are some increases of reloads in llvm-testsuite). I just want to show how many theoretical gains we can get from supporting the partial overlapping.

https://github.com/llvm/llvm-project/pull/145004