[llvm] [RISCV] Support RVV register overlapping constraints (PR #145004)

[Piyou Chen via llvm-commits]

BeMg wrote:


> 2. If we decide to support it, how to support it formally.

One idea is to overhaul the early-clobber flag and use partial early-clobber to model the correct constraints between the destination operand and source operand. This may need changes from tablegen to register allocation.


https://github.com/llvm/llvm-project/pull/145004