[llvm] [AVR] Adapt getPostIndexedAddressParts() and getPreIndexedAddressParts (PR #145040)

[Tom Vijlbrief via llvm-commits]

https://github.com/tomtor updated https://github.com/llvm/llvm-project/pull/145040

>From a9df1888755677f3b5cba65bc34927aace073c5f Mon Sep 17 00:00:00 2001
From: Tom Vijlbrief <tvijlbrief at gmail.com>
Date: Tue, 17 Jun 2025 15:11:51 +0200
Subject: [PATCH 1/3] [AVR] Adapt getPostIndexedAddressParts() and
 getPreIndexedAddressParts

Fixes https://github.com/llvm/llvm-project/issues/143247
---
 llvm/lib/Target/AVR/AVRISelLowering.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 9747ad0c5cd58..00e1fb8fd5528 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1052,6 +1052,10 @@ bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
       return false;
     }
 
+    // Fixes https://github.com/llvm/llvm-project/issues/143247
+    if (Op->getOperand(0)->hasOneUse())
+      return false;
+
     Base = Op->getOperand(0);
     Offset = DAG.getSignedConstant(RHSC, DL, MVT::i8);
     AM = ISD::PRE_DEC;
@@ -1114,6 +1118,10 @@ bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
       if (AVR::isProgramMemoryAccess(LD))
         return false;
 
+    // Fixes https://github.com/llvm/llvm-project/issues/143247
+    if (Op->getOperand(0)->hasOneUse())
+      return false;
+
     Base = Op->getOperand(0);
     Offset = DAG.getConstant(RHSC, DL, MVT::i8);
     AM = ISD::POST_INC;

>From 78ae0afbe8b4386f7f73d35bb8bb64b8c0031ce1 Mon Sep 17 00:00:00 2001
From: Tom Vijlbrief <tvijlbrief at gmail.com>
Date: Fri, 20 Jun 2025 18:26:53 +0200
Subject: [PATCH 2/3] Test Removing PreIndex case for AVR CI tests

---
 llvm/lib/Target/AVR/AVRISelLowering.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 00e1fb8fd5528..d65ef8986c98d 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1052,9 +1052,11 @@ bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
       return false;
     }
 
+#if 0 // We do not need tis for the PreIndexed case
     // Fixes https://github.com/llvm/llvm-project/issues/143247
     if (Op->getOperand(0)->hasOneUse())
       return false;
+#endif
 
     Base = Op->getOperand(0);
     Offset = DAG.getSignedConstant(RHSC, DL, MVT::i8);

>From 389e55ce2b680baab5dbf265b2e4294ecd84f37e Mon Sep 17 00:00:00 2001
From: Tom Vijlbrief <tvijlbrief at gmail.com>
Date: Sat, 21 Jun 2025 12:53:42 +0200
Subject: [PATCH 3/3] Add CI CodeGen test for AVR issue 145040

---
 llvm/test/CodeGen/AVR/issue-145040.ll | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 llvm/test/CodeGen/AVR/issue-145040.ll

diff --git a/llvm/test/CodeGen/AVR/issue-145040.ll b/llvm/test/CodeGen/AVR/issue-145040.ll
new file mode 100644
index 0000000000000..481c5fa852a1d
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/issue-145040.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -O=2 -mtriple=avr-none --mcpu=avr128db28 -verify-machineinstrs | FileCheck %s
+
+declare dso_local void @nil(i16 noundef) local_unnamed_addr addrspace(1) #1
+!3 = !{!4, !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
+
+define void @complex_sbi() {
+; CHECK: sbi 1, 7
+entry:
+  br label %while.cond
+while.cond:                                       ; preds = %while.cond, %entry
+  %s.0 = phi i16 [ 0, %entry ], [ %inc, %while.cond ]
+  %inc = add nuw nsw i16 %s.0, 1
+  %0 = load volatile i8, ptr inttoptr (i16 1 to ptr), align 1, !tbaa !3
+  %or = or i8 %0, -128
+  store volatile i8 %or, ptr inttoptr (i16 1 to ptr), align 1, !tbaa !3
+  %and = and i16 %inc, 15
+  %add = add nuw nsw i16 %and, 1
+  tail call addrspace(1) void @nil(i16 noundef %add) #2
+  br label %while.cond
+}
+