[llvm] [AVR] Adapt getPostIndexedAddressParts() and getPreIndexedAddressParts (PR #145040)
Tom Vijlbrief via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 20 09:27:06 PDT 2025
https://github.com/tomtor updated https://github.com/llvm/llvm-project/pull/145040
>From a9df1888755677f3b5cba65bc34927aace073c5f Mon Sep 17 00:00:00 2001
From: Tom Vijlbrief <tvijlbrief at gmail.com>
Date: Tue, 17 Jun 2025 15:11:51 +0200
Subject: [PATCH 1/2] [AVR] Adapt getPostIndexedAddressParts() and
getPreIndexedAddressParts
Fixes https://github.com/llvm/llvm-project/issues/143247
---
llvm/lib/Target/AVR/AVRISelLowering.cpp | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 9747ad0c5cd58..00e1fb8fd5528 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1052,6 +1052,10 @@ bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
return false;
}
+ // Fixes https://github.com/llvm/llvm-project/issues/143247
+ if (Op->getOperand(0)->hasOneUse())
+ return false;
+
Base = Op->getOperand(0);
Offset = DAG.getSignedConstant(RHSC, DL, MVT::i8);
AM = ISD::PRE_DEC;
@@ -1114,6 +1118,10 @@ bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
if (AVR::isProgramMemoryAccess(LD))
return false;
+ // Fixes https://github.com/llvm/llvm-project/issues/143247
+ if (Op->getOperand(0)->hasOneUse())
+ return false;
+
Base = Op->getOperand(0);
Offset = DAG.getConstant(RHSC, DL, MVT::i8);
AM = ISD::POST_INC;
>From 78ae0afbe8b4386f7f73d35bb8bb64b8c0031ce1 Mon Sep 17 00:00:00 2001
From: Tom Vijlbrief <tvijlbrief at gmail.com>
Date: Fri, 20 Jun 2025 18:26:53 +0200
Subject: [PATCH 2/2] Test Removing PreIndex case for AVR CI tests
---
llvm/lib/Target/AVR/AVRISelLowering.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 00e1fb8fd5528..d65ef8986c98d 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1052,9 +1052,11 @@ bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
return false;
}
+#if 0 // We do not need tis for the PreIndexed case
// Fixes https://github.com/llvm/llvm-project/issues/143247
if (Op->getOperand(0)->hasOneUse())
return false;
+#endif
Base = Op->getOperand(0);
Offset = DAG.getSignedConstant(RHSC, DL, MVT::i8);
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