[llvm] [RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (PR #145147)

[Craig Topper via llvm-commits]

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@@ -2,6 +2,174 @@
 ; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
+; NDS.BBC
+
+define i32 @bbc(i32 %a) nounwind {
+; CHECK-LABEL: bbc:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nds.bbc a0, 16, .LBB0_2
+; CHECK-NEXT:    j .LBB0_1
+; CHECK-NEXT:  .LBB0_1: # %f
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2: # %t
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    ret
+  %mask = shl i32 1, 16
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topperc wrote:

Why are we using a shift with 2 constants? Can we just write 65536 where mask is used?

https://github.com/llvm/llvm-project/pull/145147