[llvm] [RISCV] Support RVV register overlapping constraints (PR #145004)

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github-actions[bot] wrote:

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h -- llvm/include/llvm/CodeGen/LiveRegMatrix.h llvm/include/llvm/CodeGen/TargetRegisterInfo.h llvm/lib/CodeGen/LiveRegMatrix.cpp llvm/lib/CodeGen/MachineCopyPropagation.cpp llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp llvm/lib/CodeGen/RegAllocGreedy.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp llvm/lib/Target/RISCV/RISCVRegisterInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
index 64e1695e9..6c2336bae 100644
--- a/llvm/lib/CodeGen/LiveRegMatrix.cpp
+++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -259,21 +259,19 @@ LiveRegMatrix::checkInterference(const LiveInterval &VirtReg,
     return IK_VirtReg;
 
   // Check the matrix for virtual register interference.
-  bool Interference = foreachUnit(TRI, VirtReg, PhysReg,
-                                  [&](MCRegUnit Unit, const LiveRange &LR) {
-                                    LiveRange NewLR;
-                                    if (TRI->enableTargetInterference() &&
-                                        TRI->needUpdateECSlot(
-                                            LR, NewLR = copyLiveRange(LR), *LIS)) {
-                                      // Update LiveRange could make cache
-                                      // information stable. Refresh cache to
-                                      // handle it.
-                                      invalidateVirtRegs();
-                                      return query(NewLR, Unit)
-                                          .checkInterference();
-                                    } 
-                                    return query(LR, Unit).checkInterference();
-                                  });
+  bool Interference = foreachUnit(
+      TRI, VirtReg, PhysReg, [&](MCRegUnit Unit, const LiveRange &LR) {
+        LiveRange NewLR;
+        if (TRI->enableTargetInterference() &&
+            TRI->needUpdateECSlot(LR, NewLR = copyLiveRange(LR), *LIS)) {
+          // Update LiveRange could make cache
+          // information stable. Refresh cache to
+          // handle it.
+          invalidateVirtRegs();
+          return query(NewLR, Unit).checkInterference();
+        }
+        return query(LR, Unit).checkInterference();
+      });
   if (Interference)
     return IK_VirtReg;
 
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 8cf119929..138fdc861 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -921,7 +921,8 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
         // later.
         if (MO.isTied())
           ReadRegister(Reg, MI, RegularUse);
-        // If it be used by another instruction, it should not be deleted.Add commentMore actions
+        // If it be used by another instruction, it should not be deleted.Add
+        // commentMore actions
         for (const MachineOperand &UseMO : MI.uses()) {
           if (!UseMO.isReg())
             continue;

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https://github.com/llvm/llvm-project/pull/145004