[llvm] [RISCV] Support RVV register overlapping constraints (PR #145004)

[Piyou Chen via llvm-commits]

BeMg wrote:

In this PR, it models the RVV register overlapping constraints by:
1. Letting RVV pseudo instructions have a TargetConstraints attribute to retrieve the type of RVV overlapping rule
> https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#52-vector-operands
> A destination vector register group can overlap a source vector register group only if one of the following holds:
>
> * The destination EEW equals the source EEW.
> 
> * The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).
>
> * The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).
2. Provide a series of target hooks to check the real constraints in RVV instructions.
3. Extend the register allocation interference feature with target constraints to replace the early-clobber constraints.

As a result, it implements the RVV operand constraints and reduces the register pressure.

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There are some issues with this approach.

First, it breaks the early-clobber flag only at the RA stage, but other passes could be based on the early-clobber attribute to perform optimizations (for example: MachineCopyPropagation). Second, it causes several workarounds across RegAllocGreedy, LiveRegMatrix, and RegAllocEvictionAdvisor.

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I post the PR for two reason.
1. It could measure the benefit of supporting the RVV register overlapping constraints.
2. If we decide to support it, how to support it formally.

https://github.com/llvm/llvm-project/pull/145004