[llvm] [RISCV] Switch to sign-extended loads if possible in RISCVOptWInstrs (PR #144703)

[Sam Elliott via llvm-commits]

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@@ -14,25 +14,40 @@ define void @test_load_store(ptr %p, ptr %q) nounwind {
 }
 
 define float @test_fpextend_float(ptr %p) nounwind {
-; CHECK-LABEL: test_fpextend_float:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    lhu a0, 0(a0)
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    fmv.w.x fa0, a0
-; CHECK-NEXT:    ret
+; RV64-LABEL: test_fpextend_float:
+; RV64:       # %bb.0:
+; RV64-NEXT:    lh a0, 0(a0)
+; RV64-NEXT:    slli a0, a0, 16
+; RV64-NEXT:    fmv.w.x fa0, a0
+; RV64-NEXT:    ret
+;
+; RV32-LABEL: test_fpextend_float:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lhu a0, 0(a0)
+; RV32-NEXT:    slli a0, a0, 16
+; RV32-NEXT:    fmv.w.x fa0, a0
+; RV32-NEXT:    ret
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lenary wrote:

Sorry, yeah, reading this wrong.

https://github.com/llvm/llvm-project/pull/144703