[llvm] [AArch64] improve zero-cycle regmov test (PR #143680)

[Florian Hahn via llvm-commits]

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@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=arm64 | FileCheck %s -check-prefixes=CHECK,NOTCPU
+; RUN: llc < %s -march=arm64 -mcpu=apple-m1 | FileCheck %s -check-prefixes=CHECK,CPU
+; RUN: llc < %s -march=arm64 -mcpu=apple-m1 -mattr=-zcm | FileCheck %s -check-prefixes=CHECK,NOTATTR
+; RUN: llc < %s -march=arm64 -mattr=+zcm | FileCheck %s -check-prefixes=CHECK,ATTR
+
+define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind ssp {
+entry:
+; CHECK-LABEL: t:
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fhahn wrote:

> So CPU/ATTR differ because -mcpu changes the order of instructions. Same for NOTATTR/NOTCPU. I can separate each configuration by duplicating ; CHECK: bl {{_?foo}}, or autogen it.

Ah I see, thanks. Separating the output makes things clearer.

https://github.com/llvm/llvm-project/pull/143680