[llvm] [AArch64] improve zero-cycle regmov test (PR #143680)

[Florian Hahn via llvm-commits]

================
@@ -0,0 +1,45 @@
+; RUN: llc < %s -march=arm64 | FileCheck %s -check-prefixes=NOTCPU --match-full-lines
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=CPU --match-full-lines
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm | FileCheck %s -check-prefixes=NOTATTR --match-full-lines
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm | FileCheck %s -check-prefixes=ATTR --match-full-lines
+
+define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) {
----------------
fhahn wrote:

```suggestion
define void @t(i32 %a, i32 %b, i32 %c, i32 %d) {
```

nothing returned

https://github.com/llvm/llvm-project/pull/143680