[llvm] [RISCV] Guard the alternative static chain register use on RV32E (PR #142715)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Jesse Huang (jaidTw)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/142715.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVCallingConv.cpp (+4) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index e0d1fb2facc87..3b609adcf8c09 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -338,6 +338,10 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   bool HasCFBranch =
       Subtarget.hasStdExtZicfilp() &&
       MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
+  if (HasCFBranch && (Subtarget.isRV32() && Subtarget.hasStdExtE()))
+    reportFatalUsageError(
+        "Alternative static chain register is not supported on RV32E");
+
   // Normal: t2, Branch control flow protection: t3
   const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/142715