[llvm] [RISCV] Guard the alternative static chain register use on RV32E (PR #142715)

[Craig Topper via llvm-commits]

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@@ -338,6 +338,10 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   bool HasCFBranch =
       Subtarget.hasStdExtZicfilp() &&
       MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
+  if (HasCFBranch && (Subtarget.isRV32() && Subtarget.hasStdExtE()))
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topperc wrote:

It's just as broken for RV64E too right?

https://github.com/llvm/llvm-project/pull/142715