[llvm] [RISCV] Guard the alternative static chain register use on RV32E (PR #142715)

[Jesse Huang via llvm-commits]

https://github.com/jaidTw created https://github.com/llvm/llvm-project/pull/142715

None

>From 20866709d984cc17a9aa8fd9438c923c1c201aa7 Mon Sep 17 00:00:00 2001
From: Jesse Huang <jesse.huang at sifive.com>
Date: Tue, 3 Jun 2025 21:55:37 -0700
Subject: [PATCH] [RISCV] Guard the alternative static chain register use on
 RV32E

---
 llvm/lib/Target/RISCV/RISCVCallingConv.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index e0d1fb2facc87..3b609adcf8c09 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -338,6 +338,10 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   bool HasCFBranch =
       Subtarget.hasStdExtZicfilp() &&
       MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
+  if (HasCFBranch && (Subtarget.isRV32() && Subtarget.hasStdExtE()))
+    reportFatalUsageError(
+        "Alternative static chain register is not supported on RV32E");
+
   // Normal: t2, Branch control flow protection: t3
   const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;