[llvm] [RISCV] Use t3 for static chain register when branch CFI is enabled (PR #142344)

Jessica Clarke via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 2 12:34:10 PDT 2025

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jrtc27 wrote:

Isn't this incompatible with RV32E now?

https://github.com/llvm/llvm-project/pull/142344

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