[llvm] [DAG] canCreateUndefOrPoison – mark fneg/fadd/fsub/fmul/fdiv/frem as not poison generating (PR #142345)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 2 01:18:05 PDT 2025
https://github.com/harrisonGPU created https://github.com/llvm/llvm-project/pull/142345
After revisiting the LLVM Language Reference Manual, it is confirmed that
plain floating-point operations (`fneg`, `fadd`, `fsub`, `fmul`, `fdiv`, and `frem`)
propagate poison but do not inherently create new poison values. Thus,
`SelectionDAG::canCreateUndefOrPoison` should return `false` for these
operations by default.
Poison generation in FP instructions occurs only when specific fast-math
flags (`nnan`, `ninf`, or the collective fast) are present, as these flags
explicitly convert NaN or Inf results into poison.
References:
- [`fneg` instruction documentation](https://llvm.org/docs/LangRef.html#fneg-instruction)
- [`fadd` instruction documentation](https://llvm.org/docs/LangRef.html#fadd-instruction)
- [`fsub` instruction documentation](https://llvm.org/docs/LangRef.html#fsub-instruction)
- [`fmul` instruction documentation](https://llvm.org/docs/LangRef.html#fmul-instruction)
- [`fdiv` instruction documentation](https://llvm.org/docs/LangRef.html#fdiv-instruction)
- [`frem` instruction documentation](https://llvm.org/docs/LangRef.html#frem-instruction)
- [Fast-Math Flags documentation](https://llvm.org/docs/LangRef.html#fast-math-flags)
>From 3cc4a4c5ab260a9bd718ade51fc1495954c16597 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Sun, 1 Jun 2025 14:08:43 +0000
Subject: [PATCH] =?UTF-8?q?[DAG]=20canCreateUndefOrPoison=20=E2=80=93=20ma?=
=?UTF-8?q?rk=20fneg/fadd/fsub/fmul/fdiv/frem=20as=20not=20poison=20genera?=
=?UTF-8?q?ting?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 +
llvm/test/CodeGen/AMDGPU/freeze-binary.ll | 282 ++++++++++++++++++
2 files changed, 288 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/freeze-binary.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1506bc4ee187d..279c7daf71c33 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5579,6 +5579,12 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
+ case ISD::FNEG:
+ case ISD::FADD:
+ case ISD::FSUB:
+ case ISD::FMUL:
+ case ISD::FDIV:
+ case ISD::FREM:
// No poison except from flags (which is handled above)
return false;
diff --git a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
new file mode 100644
index 0000000000000..4321cedcc8b96
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -0,0 +1,282 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
+define float @freeze_fadd(float %input) nounwind {
+; GFX11-LABEL: freeze_fadd:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v0, 2.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
+ ret float %z
+}
+
+define float @freeze_fadd_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fadd_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fadd nnan contract float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fadd nnan contract float %y, 1.000000e+00
+ ret float %z
+}
+
+define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fadd_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
+; GFX11-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ %y = freeze <4 x float> %x
+ %z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ ret <4 x float> %z
+}
+
+define float @freeze_fsub(float %input) nounwind {
+; GFX11-LABEL: freeze_fsub:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+00
+ ret float %z
+}
+
+define float @freeze_fsub_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fsub_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fsub nnan contract float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fsub nnan contract float %y, 1.000000e+00
+ ret float %z
+}
+
+define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fsub_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
+; GFX11-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ %y = freeze <4 x float> %x
+ %z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ ret <4 x float> %z
+}
+
+define float @freeze_fmul(float %input) nounwind {
+; GFX11-LABEL: freeze_fmul:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 4.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+00
+ ret float %z
+}
+
+define float @freeze_fmul_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fmul_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fmul nnan contract float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fmul nnan contract float %y, 2.000000e+00
+ ret float %z
+}
+
+define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fmul_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
+; GFX11-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
+; GFX11-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
+; GFX11-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ %y = freeze <8 x float> %x
+ %z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ ret <8 x float> %z
+}
+
+define float @freeze_fdiv(float %input) nounwind {
+; GFX11-LABEL: freeze_fdiv:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00
+ ret float %z
+}
+
+define float @freeze_fdiv_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fdiv_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fdiv nnan contract float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fdiv nnan contract float %y, 2.000000e+00
+ ret float %z
+}
+
+define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fdiv_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
+; GFX11-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
+; GFX11-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
+; GFX11-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ %y = freeze <8 x float> %x
+ %z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ ret <8 x float> %z
+}
+
+define float @freeze_frem(float %input) nounwind {
+; GFX11-LABEL: freeze_frem:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v1, v1
+; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00
+ ret float %z
+}
+
+define float @freeze_frem_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_frem_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v1, v1
+; GFX11-NEXT: v_fma_f32 v1, -2.0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v2, v2
+; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = frem nnan contract float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = frem nnan contract float %y, 2.000000e+00
+ ret float %z
+}
+
+define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_frem_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
+; GFX11-NEXT: v_trunc_f32_e32 v11, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_trunc_f32_e32 v8, v8
+; GFX11-NEXT: v_trunc_f32_e32 v9, v9
+; GFX11-NEXT: v_mul_f32_e32 v10, 0.5, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
+; GFX11-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v10, v10
+; GFX11-NEXT: v_trunc_f32_e32 v9, v7
+; GFX11-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
+; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v1
+; GFX11-NEXT: v_trunc_f32_e32 v9, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
+; GFX11-NEXT: v_trunc_f32_e32 v8, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v8
+; GFX11-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
+; GFX11-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v8, v10
+; GFX11-NEXT: v_trunc_f32_e32 v10, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
+; GFX11-NEXT: v_trunc_f32_e32 v8, v11
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
+; GFX11-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_fmac_f32_e32 v7, -4.0, v8
+; GFX11-NEXT: v_trunc_f32_e32 v9, v12
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
+; GFX11-NEXT: v_trunc_f32_e32 v9, v11
+; GFX11-NEXT: v_trunc_f32_e32 v11, v3
+; GFX11-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_trunc_f32_e32 v8, v10
+; GFX11-NEXT: v_trunc_f32_e32 v10, v12
+; GFX11-NEXT: v_trunc_f32_e32 v12, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_fmac_f32_e32 v2, -2.0, v8
+; GFX11-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_sub_f32_e32 v4, v4, v12
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ %y = freeze <8 x float> %x
+ %z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ ret <8 x float> %z
+}
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