[llvm] [SelectionDAG][Darwin] Convert insert 0 to AND with bitmask (PR #142428)

[Florian Hahn via llvm-commits]

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@@ -26057,11 +26057,67 @@ static SDValue removeRedundantInsertVectorElt(SDNode *N) {
   return ExtractVec;
 }
 
+// On Darwin, instead of explictly inserting 0 into a vector, which results in
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fhahn wrote:

Referencing darwin here is a bit confusing, as this isn't a property of the platform but of the CPUs. Also should the comment go to the code that actually does the check?


https://github.com/llvm/llvm-project/pull/142428