[llvm] [SelectionDAG][Darwin] Convert insert 0 to AND with bitmask (PR #142428)

[Florian Hahn via llvm-commits]

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@@ -26057,11 +26057,67 @@ static SDValue removeRedundantInsertVectorElt(SDNode *N) {
   return ExtractVec;
 }
 
+// On Darwin, instead of explictly inserting 0 into a vector, which results in
+// a costly move from an integer to a vector register, use a bitmask to zero
+// out the corresponding lane.
+static SDValue convertInsertVectorEltToAnd(SDNode *N, SelectionDAG &DAG,
+                                           const AArch64Subtarget *Subtarget) {
+  assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && "Unexpected node!");
+
+  if (!Subtarget->isTargetDarwin())
+    return SDValue();
+
+  SDValue InsertVec = N->getOperand(0);
+  SDValue InsertVal = N->getOperand(1);
+  SDValue InsertIdx = N->getOperand(2);
+
+  ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(InsertIdx);
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fhahn wrote:

move closer to check

https://github.com/llvm/llvm-project/pull/142428