[llvm] [SelectionDAG][Darwin] Convert insert 0 to AND with bitmask (PR #142428)

[Florian Hahn via llvm-commits]

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@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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fhahn wrote:

Do the existing tests cover all checks in the code? Might be good to at least have some tests with different vector sizes, including > 128 bits and odd number of elements.

https://github.com/llvm/llvm-project/pull/142428