[llvm] b754e40 - MC: Remove redundant relocations for label differences
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sat May 24 17:41:03 PDT 2025
Author: Fangrui Song
Date: 2025-05-24T17:40:59-07:00
New Revision: b754e4085541df750c51677e522dd939e2aa9e2d
URL: https://github.com/llvm/llvm-project/commit/b754e4085541df750c51677e522dd939e2aa9e2d
DIFF: https://github.com/llvm/llvm-project/commit/b754e4085541df750c51677e522dd939e2aa9e2d.diff
LOG: MC: Remove redundant relocations for label differences
For the label difference A-B where A and B are in the same section,
if the section contains no linker-relaxable instruction, we can disable
the framnent walk code path (https://reviews.llvm.org/D155357), removing
redundant relocations. This optimization is available since we now track
per-section linker-relaxable instructions (#140692).
lld/test/ELF/loongarch-reloc-leb128.s , introduced in #81133, has been
updated in 9662a6039c0320eb4473d87b47f0ed891a0f111c to prevent coverage
loss.
Added:
Modified:
llvm/include/llvm/MC/MCAsmBackend.h
llvm/lib/MC/MCAsmBackend.cpp
llvm/lib/MC/MCExpr.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/test/MC/RISCV/Relocations/align-non-executable.s
llvm/test/MC/RISCV/Relocations/leb128.s
llvm/test/MC/RISCV/cfi-advance.s
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCAsmBackend.h b/llvm/include/llvm/MC/MCAsmBackend.h
index 325468d0f5187..3b095772bd144 100644
--- a/llvm/include/llvm/MC/MCAsmBackend.h
+++ b/llvm/include/llvm/MC/MCAsmBackend.h
@@ -41,7 +41,7 @@ class raw_ostream;
/// Generic interface to target specific assembler backends.
class MCAsmBackend {
protected: // Can only create subclasses.
- MCAsmBackend(llvm::endianness Endian, bool LinkerRelaxation = false);
+ MCAsmBackend(llvm::endianness Endian) : Endian(Endian) {}
MCAssembler *Asm = nullptr;
@@ -56,10 +56,6 @@ class MCAsmBackend {
MCContext &getContext() const;
- /// True for RISC-V and LoongArch. Relaxable relocations are marked with a
- /// RELAX relocation.
- bool allowLinkerRelaxation() const { return LinkerRelaxation; }
-
/// Return true if this target might automatically pad instructions and thus
/// need to emit padding enable/disable directives around sensative code.
virtual bool allowAutoPadding() const { return false; }
@@ -216,9 +212,6 @@ class MCAsmBackend {
// Return STI for fragments of type MCRelaxableFragment and MCDataFragment
// with hasInstructions() == true.
static const MCSubtargetInfo *getSubtargetInfo(const MCFragment &F);
-
-private:
- const bool LinkerRelaxation;
};
} // end namespace llvm
diff --git a/llvm/lib/MC/MCAsmBackend.cpp b/llvm/lib/MC/MCAsmBackend.cpp
index 4c803585ce25c..c69e42dfc9fe6 100644
--- a/llvm/lib/MC/MCAsmBackend.cpp
+++ b/llvm/lib/MC/MCAsmBackend.cpp
@@ -24,9 +24,6 @@
using namespace llvm;
-MCAsmBackend::MCAsmBackend(llvm::endianness Endian, bool LinkerRelaxation)
- : Endian(Endian), LinkerRelaxation(LinkerRelaxation) {}
-
MCAsmBackend::~MCAsmBackend() = default;
MCContext &MCAsmBackend::getContext() const { return Asm->getContext(); }
diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
index f890e477adf94..bb2c7a98ed67c 100644
--- a/llvm/lib/MC/MCExpr.cpp
+++ b/llvm/lib/MC/MCExpr.cpp
@@ -319,12 +319,11 @@ static void attemptToFoldSymbolOffsetDifference(const MCAssembler *Asm,
// When layout is available, we can generally compute the
diff erence using the
// getSymbolOffset path, which also avoids the possible slow fragment walk.
// However, linker relaxation may cause incorrect fold of A-B if A and B are
- // separated by a linker-relaxable instruction. If the section contains
- // instructions and InSet is false (not expressions in directive like
- // .size/.fill), disable the fast path.
+ // separated by a linker-relaxable fragment. If the section contains
+ // linker-relaxable instruction and InSet is false (not expressions in
+ // directive like .size/.fill), disable the fast path.
bool Layout = Asm->hasLayout();
- if (Layout && (InSet || !SecA.hasInstructions() ||
- !Asm->getBackend().allowLinkerRelaxation())) {
+ if (Layout && (InSet || !SecA.isLinkerRelaxable())) {
// If both symbols are in the same fragment, return the
diff erence of their
// offsets. canGetFragmentOffset(FA) may be false.
if (FA == FB && !SA.isVariable() && !SB.isVariable()) {
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
index 7d529ed06f302..d7569ab0ea597 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
@@ -31,8 +31,8 @@ using namespace llvm;
LoongArchAsmBackend::LoongArchAsmBackend(const MCSubtargetInfo &STI,
uint8_t OSABI, bool Is64Bit,
const MCTargetOptions &Options)
- : MCAsmBackend(llvm::endianness::little, /*LinkerRelaxation=*/true),
- STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {}
+ : MCAsmBackend(llvm::endianness::little), STI(STI), OSABI(OSABI),
+ Is64Bit(Is64Bit), TargetOptions(Options) {}
std::optional<MCFixupKind>
LoongArchAsmBackend::getFixupKind(StringRef Name) const {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index ff647d4c7fc0c..f7f39439249e8 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -37,8 +37,8 @@ static cl::opt<bool> ULEB128Reloc(
RISCVAsmBackend::RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI,
bool Is64Bit, const MCTargetOptions &Options)
- : MCAsmBackend(llvm::endianness::little, /*LinkerRelaxation=*/true),
- STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
+ : MCAsmBackend(llvm::endianness::little), STI(STI), OSABI(OSABI),
+ Is64Bit(Is64Bit), TargetOptions(Options) {
RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
}
diff --git a/llvm/test/MC/RISCV/Relocations/align-non-executable.s b/llvm/test/MC/RISCV/Relocations/align-non-executable.s
index 95f91d93369f2..299f110b65698 100644
--- a/llvm/test/MC/RISCV/Relocations/align-non-executable.s
+++ b/llvm/test/MC/RISCV/Relocations/align-non-executable.s
@@ -19,7 +19,7 @@
# CHECK-NEXT: Section ({{.*}}) .rela.dummy {
# CHECK-NEXT: 0x0 R_RISCV_CALL_PLT func 0x0
# RELAX-NEXT: 0x0 R_RISCV_RELAX - 0x0
-# CHECK-NEXT: 0x8 R_RISCV_ADD64 .L2 0x0
-# CHECK-NEXT: 0x8 R_RISCV_SUB64 .L1 0x0
+# RELAX-NEXT: 0x8 R_RISCV_ADD64 .L2 0x0
+# RELAX-NEXT: 0x8 R_RISCV_SUB64 .L1 0x0
# CHECK-NEXT: }
# CHECK-NEXT: ]
diff --git a/llvm/test/MC/RISCV/Relocations/leb128.s b/llvm/test/MC/RISCV/Relocations/leb128.s
index 429eac6971822..b765e3d56f111 100644
--- a/llvm/test/MC/RISCV/Relocations/leb128.s
+++ b/llvm/test/MC/RISCV/Relocations/leb128.s
@@ -29,8 +29,8 @@
# CHECK: Relocations [
# CHECK-NEXT: .rela.alloc_w {
-# CHECK-NEXT: 0x0 R_RISCV_SET_ULEB128 w1 0x0
-# CHECK-NEXT: 0x0 R_RISCV_SUB_ULEB128 w 0x0
+# RELAX-NEXT: 0x0 R_RISCV_SET_ULEB128 w1 0x0
+# RELAX-NEXT: 0x0 R_RISCV_SUB_ULEB128 w 0x0
# RELAX-NEXT: 0x1 R_RISCV_SET_ULEB128 w2 0x0
# RELAX-NEXT: 0x1 R_RISCV_SUB_ULEB128 w1 0x0
# CHECK-NEXT: 0x2 R_RISCV_CALL_PLT foo 0x0
diff --git a/llvm/test/MC/RISCV/cfi-advance.s b/llvm/test/MC/RISCV/cfi-advance.s
index 1d00214da46c6..1f49abbccf5e2 100644
--- a/llvm/test/MC/RISCV/cfi-advance.s
+++ b/llvm/test/MC/RISCV/cfi-advance.s
@@ -1,41 +1,28 @@
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax %s -o %t.o
-# RUN: llvm-readelf -sr %t.o | FileCheck %s --check-prefix=NORELAX
+# RUN: llvm-readelf -sr %t.o | FileCheck %s --check-prefixes=CHECK,NORELAX
# RUN: llvm-dwarfdump --debug-frame %t.o 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-DWARFDUMP %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax %s -o %t.relax.o
-# RUN: llvm-readelf -sr %t.relax.o | FileCheck %s --check-prefix=RELAX
+# RUN: llvm-readelf -sr %t.relax.o | FileCheck %s --check-prefixes=CHECK,RELAX
# NORELAX: Relocation section '.rela.text1' at offset {{.*}} contains 1 entries:
# NORELAX-NEXT: Offset Info Type Sym. Value Symbol's Name + Addend
# NORELAX-NEXT: 00000000 00000313 R_RISCV_CALL_PLT 00000004 .L0 + 0
# NORELAX-EMPTY:
-# NORELAX-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 1 entries:
-# NORELAX: Offset Info Type Sym. Value Symbol's Name + Addend
-# NORELAX-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0
-# NORELAX-EMPTY:
-# NORELAX: Symbol table '.symtab' contains 13 entries:
-# NORELAX-NEXT: Num: Value Size Type Bind Vis Ndx Name
-# NORELAX-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
-# NORELAX-NEXT: 1: 00000000 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}}
-# NORELAX: 3: 00000004 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}}
-# NORELAX-NOT: .L0
-
-# RELAX: Relocation section '.rela.eh_frame' at offset {{.*}} contains 5 entries:
-# RELAX-NEXT: Offset Info Type Sym. Value Symbol's Name + Addend
-# RELAX-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0
-# RELAX-NEXT: 00000020 00000c23 R_RISCV_ADD32 0001017a .L0 + 0
-# RELAX-NEXT: 00000020 00000127 R_RISCV_SUB32 00000000 .L0 + 0
-# RELAX-NEXT: 00000035 00000b35 R_RISCV_SET6 00010176 .L0 + 0
-# RELAX-NEXT: 00000035 00000934 R_RISCV_SUB6 0001016e .L0 + 0
+# RELAX: Relocation section '.rela.text1' at offset {{.*}} contains 2 entries:
+# RELAX: R_RISCV_CALL_PLT
+# RELAX-NEXT: R_RISCV_RELAX
# RELAX-EMPTY:
-# RELAX: Symbol table '.symtab' contains 16 entries:
-# RELAX-NEXT: Num: Value Size Type Bind Vis Ndx Name
-# RELAX-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
-# RELAX-NEXT: 1: 00000000 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}}
-# RELAX: 3: 00000004 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}}
-# RELAX: 9: 0001016e 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}}
-# RELAX: 11: 00010176 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}}
-# RELAX: 12: 0001017a 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}}
+# CHECK-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 1 entries:
+# CHECK: Offset Info Type Sym. Value Symbol's Name + Addend
+# CHECK-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0
+# CHECK-EMPTY:
+# CHECK: Symbol table '.symtab' contains 13 entries:
+# CHECK-NEXT: Num: Value Size Type Bind Vis Ndx Name
+# CHECK-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
+# CHECK-NEXT: 1: 00000000 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}}
+# CHECK: 3: 00000004 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}}
+# CHECK-NOT: .L0
# CHECK-DWARFDUMP: DW_CFA_advance_loc1: 104
# CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8
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