[llvm] [MachineScheduler][AArch64] Skip Neoverse V2 Pre-RA MISched for large vector intrinsic codes (PR #139557)

[Sjoerd Meijer via llvm-commits]

sjoerdmeijer wrote:

Hi @arsenm, thanks a lot for your review! I am going to abandon this work, because we've found a less intrusive way of fixing the issue that we're trying to fix, i.e. the fix in https://github.com/llvm/llvm-project/pull/140897 sets a subtarget feature FeatureDisableLatencySchedHeuristic that does the trick.

https://github.com/llvm/llvm-project/pull/139557