[llvm] [WIP][AMDGPU][MC] Support 128b rsrc reg in mimg instructions (PR #139121)

[Jun Wang via llvm-commits]

================
@@ -3974,6 +3975,64 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
   return false;
 }
 
+bool AMDGPUAsmParser::validateMIMGR128(const MCInst &Inst,
+                                       const OperandVector &Operands) {
+  const unsigned Opc = Inst.getOpcode();
+  const MCInstrDesc &Desc = MII.get(Opc);
+
+  if ((Desc.TSFlags & MIMGFlags) == 0)
+    return true;
+
+  // image_bvh_intersect_ray instructions only support 128b RSRC reg
+  if (AMDGPU::getMIMGBaseOpcode(Opc)->BVH)
+    return true;
+
+  AMDGPU::OpName RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG)
+                                  ? AMDGPU::OpName::srsrc
+                                  : AMDGPU::OpName::rsrc;
+  int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
+  assert(SrsrcIdx != -1);
+
+  auto RsrcReg = Inst.getOperand(SrsrcIdx).getReg();
+
+  unsigned SrsrcRegSize = 4;
+  if (getMRI()->getRegClass(AMDGPU::SReg_256_XNULLRegClassID).contains(RsrcReg))
+    SrsrcRegSize = 8;
+  else {
+    switch (RsrcReg.id()) {
+    case TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_vi:
+    case TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_vi:
+    case TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi:
+    case TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_gfx9plus:
+    case TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_gfx9plus:
+    case TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus:
+      SrsrcRegSize = 8;
+      break;
----------------
jwanggit86 wrote:

In `getMCReg()`, registers such as TTMP0_TTMP1..._TTMP7 are converted to the ones with a suffix "_vi" or "_gfx9plus". Those new registers don't seem to belong to any reg class.

https://github.com/llvm/llvm-project/pull/139121