[llvm] [WIP][AMDGPU][MC] Support 128b rsrc reg in mimg instructions (PR #139121)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 2bb691008..6d0bf9e94 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4026,8 +4026,7 @@ bool AMDGPUAsmParser::validateMIMGR128(const MCInst &Inst,
   if (SrsrcRegSize == 4 && !IsR128) {
     auto Loc = getInstLoc(Operands);
     if (hasMIMG_R128())
-      Error(Loc,
-            "rsrc reg should be 256-bit, or the r128 flag is required");
+      Error(Loc, "rsrc reg should be 256-bit, or the r128 flag is required");
     else
       Error(Loc, "operands are not valid for this GPU or mode");
     return false;

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https://github.com/llvm/llvm-project/pull/139121