[llvm] [CodeGen] Add assertion to MachineBasicBlock::addLiveIn and friends (PR #140527)

[Jay Foad via llvm-commits]

================
@@ -503,7 +503,8 @@ bool RegAllocFastImpl::mayBeSpillFromInlineAsmBr(const MachineInstr &MI) const {
   if (MBB->isInlineAsmBrIndirectTarget() && TII->isStoreToStackSlot(MI, FI) &&
       MFI->isSpillSlotObjectIndex(FI))
     for (const auto &Op : MI.operands())
-      if (Op.isReg() && MBB->isLiveIn(Op.getReg()))
+      if (Op.isReg() && Op.getReg() != MCRegister::NoRegister &&
+          MBB->isLiveIn(Op.getReg()))
----------------
jayfoad wrote:

I am not convinced this is the right place to do this. It avoids failures in a couple of MIR tests which have `$noreg` in the input:
```
Failed Tests (2):
  LLVM :: CodeGen/X86/callbr-asm-outputs-regallocfast.mir
  LLVM :: CodeGen/X86/regallocfast-callbr-asm-spills-after-reload.mir
```

https://github.com/llvm/llvm-project/pull/140527