[llvm] [WIP][CodeGen] Modifying MBB's liveins representation as into regUnits (PR #129847)

[Vikash Gupta via llvm-commits]

================
@@ -174,8 +176,7 @@ class MachineBasicBlock
   std::optional<uint64_t> IrrLoopHeaderWeight;
 
   /// Keep track of the physical registers that are livein of the basicblock.
-  using LiveInVector = std::vector<RegisterMaskPair>;
-  LiveInVector LiveIns;
+  DenseSet<MCRegister> LiveIns;
----------------
vg0204 wrote:

> I'm not sure if it's a good idea to change from std::vector to DenseSet. The patch would be less invasive if you just changed it to std:vector<MCRegister>

It makes sense so aliasing registers (or tuples) will have common regunits (or their roots) to track them uniquely (in set) and check for isLiveIn would be cheaper.


> You should at least benchmark it using http://llvm-compile-time-tracker.com/. You can do this by asking @nikic to add your fork of LLVM, and then any branches you create called "perf/*" will automatically get benchmarked.

Sure!

https://github.com/llvm/llvm-project/pull/129847