[llvm] [PowerPC] Update DMF VSX ACC data transfer instructions (PR #138897)

[via llvm-commits]

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@@ -535,25 +535,25 @@ let Predicates = [MMA, IsNotISAFuture] in {
 }
 
 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
-  // For Future and up XXMFACCW and XXMTACCW will not have patterns.
   // On Future CPU the wacc registers no longer overlap with the vsr registers
-  // and so register allocation would have to know to match 4 vsr registers
-  // with one wacc register.
-  // On top of that Future CPU has a more convenient way to move between vsrs
-  // and wacc registers using xxextfdmr512 and xxinstdmr512.
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RolandF77 wrote:

I don't think we should add patterns for DMXXMTACC/DMXXMFACC for ISA Future, and I don't think we should change the comment. Lowering will replace these intrinsic calls.

https://github.com/llvm/llvm-project/pull/138897