[llvm] 711d72e - [LLVM][SVE] Relax optimizeIncrementingWhile constant operand requirements. (#140037)

[via llvm-commits]

Author: Paul Walker
Date: 2025-05-16T11:43:56+01:00
New Revision: 711d72e38ecc5a9b605ae9bf2dbc9c3f34d8aca5

URL: https://github.com/llvm/llvm-project/commit/711d72e38ecc5a9b605ae9bf2dbc9c3f34d8aca5
DIFF: https://github.com/llvm/llvm-project/commit/711d72e38ecc5a9b605ae9bf2dbc9c3f34d8aca5.diff

LOG: [LLVM][SVE] Relax optimizeIncrementingWhile constant operand requirements. (#140037)

Only the latter part of optimizeIncrementingWhile requires a constant
first operand and so the initial bailout code is preventing the obvious
whilele(X,MAX_INT) -> splat(true) combine.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index fb7f7d6f7537d..c7858e4106358 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5744,12 +5744,10 @@ static SDValue optimizeIncrementingWhile(SDNode *N, SelectionDAG &DAG,
   unsigned Op0 = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 1 : 0;
   unsigned Op1 = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 2 : 1;
 
-  if (!isa<ConstantSDNode>(N->getOperand(Op0)) ||
-      !isa<ConstantSDNode>(N->getOperand(Op1)))
+  if (!isa<ConstantSDNode>(N->getOperand(Op1)))
     return SDValue();
 
   SDLoc dl(N);
-  APInt X = N->getConstantOperandAPInt(Op0);
   APInt Y = N->getConstantOperandAPInt(Op1);
 
   // When the second operand is the maximum value, comparisons that include
@@ -5758,6 +5756,11 @@ static SDValue optimizeIncrementingWhile(SDNode *N, SelectionDAG &DAG,
     if (IsSigned ? Y.isMaxSignedValue() : Y.isMaxValue())
       return DAG.getConstant(1, dl, N->getValueType(0));
 
+  if (!isa<ConstantSDNode>(N->getOperand(Op0)))
+    return SDValue();
+
+  APInt X = N->getConstantOperandAPInt(Op0);
+
   bool Overflow;
   APInt NumActiveElems =
       IsSigned ? Y.ssub_ov(X, Overflow) : Y.usub_ov(X, Overflow);

diff  --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll
index ab4554428be45..a82998473fe68 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll
@@ -128,12 +128,12 @@ define <vscale x 16 x i1> @whilele_b_ii_dont_fold_to_ptrue_overflow() {
   ret <vscale x 16 x i1> %out
 }
 
-define <vscale x 16 x i1> @whilele_b_ii_known_always_true() {
+define <vscale x 16 x i1> @whilele_b_ii_known_always_true(i32 %a) {
 ; CHECK-LABEL: whilele_b_ii_known_always_true:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    ret
-  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 2147483646, i32 2147483647)
+  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %a, i32 2147483647)
   ret <vscale x 16 x i1> %out
 }
 
@@ -387,12 +387,12 @@ define <vscale x 16 x i1> @whilels_b_ii_dont_fold_to_ptrue_overflow() {
   ret <vscale x 16 x i1> %out
 }
 
-define <vscale x 16 x i1> @whilels_b_ii_known_always_true() {
+define <vscale x 16 x i1> @whilels_b_ii_known_always_true(i32 %a) {
 ; CHECK-LABEL: whilels_b_ii_known_always_true:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    ret
-  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 4294967294, i32 4294967295)
+  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %a, i32 4294967295)
   ret <vscale x 16 x i1> %out
 }