[llvm] [LLVM][AArch64] Correctly lower funnel shifts by zero. (PR #140058)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

> But I'm not entirely clear what you're trying to handle here - does arm64 only support FSHR nodes with constant shift amounts? What happens with zero / modulo amounts with that instruction that is so bad?

Continuing on from what David said above, it's not that FSHR does not like zero, but that the custom lowering code tries to rewrite all FSHLs with constant shift amounts as FSHRs because isel only exists for the latter.  The problem being the transformation is invalid when the modulo shift amount is 0.  Whilst fixing that I spotted the FSHR AArch64 isel rules only support [0-BitWidth) so I figured I'd fix that as well so that we can be sure the lowered result can be isel'd.

https://github.com/llvm/llvm-project/pull/140058