[llvm] [RISCV] Use RISCVRegisterInfo::isRVVRegClass to replace IsScalableVector in storeRegToStackSlot/loadRegFromStackSlot. NFC (PR #139979)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Thu May 15 08:34:57 PDT 2025

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https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/139979

Previous message: [llvm] [RISCV] Use RISCVRegisterInfo::isRVVRegClass to replace IsScalableVector in storeRegToStackSlot/loadRegFromStackSlot. NFC (PR #139979)
Next message: [llvm] [InlineCost]: Optimize inlining of recursive function. (PR #139982)
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