[llvm] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT operations. (PR #112647)

[Harrison Hao via llvm-commits]

================
@@ -17561,3 +17561,13 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
   AI->eraseFromParent();
   return LI;
 }
+
+bool SITargetLowering::hasAndNot(SDValue Op) const {
----------------
harrisonGPU wrote:

Thank you for your comments. Since `SIISelLowering.cpp` already targets GCN exclusively, the extra guard doesn’t add much. R600 code lives in `AMDGPUTargetLowering.cpp` anyway.

https://github.com/llvm/llvm-project/pull/112647